SST39VF3201C-70-4I-B3KE

The SST39VF3201C/3202C also have the Auto Low Power mode which puts the device in a near

read current from typically 9 mA to typically 4 µA. The Auto Low Power mode reduces the typical I

active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power

mode with any address transition or control signal transition used to initiate another Read cycle, with

no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with

CE# held steadily low, until the first address transition or CE# is driven high.

Refer to the Read cycle timing diagram for further details (Figure 5).

The SST39VF3201C/3202C are programmed on a word-by-word basis. Before programming, the sector

where the word exists must be fully erased. The Program operation is accomplished in three steps.

The first step is the three-byte load sequence for Software Data Protection. The second step is to load

word address and word data. During the Word-Program operation, the addresses are latched on the

falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of

either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is ini-

tiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation,

once initiated, will be completed within 10 µs. See Figure 6 and Figure 7 for WE# and CE# controlled

Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the

only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is

block sizes of 4 and 32 KWord. The Sector-Erase operation is initiated by executing a six-byte com-

mand sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The

Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase com-

mand (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the

falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of

the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase

operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 11 and Fig-

ure 12 for timing waveforms and Figure 25 for the flowchart. Any commands issued during the Sector-

or Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the pro-

tected block will be ignored. During the command sequence, WP# should be statically held high or low.

suspended from an Erase operation. Reading at address location within erase-suspended sectors/

blocks will output DQ

tion is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue

Erase Resume command. The operation is executed by issuing one byte command sequence with

Erase Resume command (30H) at any address in the last Byte sequence.

The SST39VF3201C/3202C provide a Chip-Erase operation, which allows the user to erase the entire

memory array to the “1” state. This is useful when the entire device must be quickly erased.

be statically held high or low.

The SST39VF3201C/3202C provide two software means to detect the completion of a Write (Program

or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two

status bits: Data# Polling (DQ

after the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a

Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this

occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with