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LTC2282IUP#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC2282
10
2282fb
TIMING DIAGRAMS
t
APB
B + 1
B + 2
B + 4
B + 3
B
ANALOG
INPUT B
t
APA
A + 1
A – 5
B – 5
B – 5
A – 5
A – 4
B – 4
B – 4
A – 4
A – 3
B – 3
B – 3
A – 3
A – 2
B – 2
B – 2
A – 2
A – 1
B – 1
A + 2
A + 4
A + 3
A
ANALOG
INPUT A
t
H
t
D
t
MD
t
L
CLKA = CLKB = MUX
D0A-D11A, OFA
2282 TD02
D0B-D11B, OFB
t
AP
N + 1
N + 2
N + 4
N + 3
N + 5
N
ANALOG
INPUT
t
H
t
D
t
L
N – 4 N – 3 N – 2 N – 1
CLK
D0-D11, OF
2282 TD01
N – 5
N
Dual Digital Output Bus Timing
(Only One Channel is Shown)
Multiplexed Digital Output Bus Timing
LTC2282
11
2282fb
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is
the ratio between the RMS amplitude of the fundamen-
tal input frequency and the RMS amplitude of all other
frequency components at the ADC output. The output is
band limited to frequencies above DC to below half the
sampling frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the fi rst fi ve harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD = 20Log (√(V2
2
+ V3
2
+ V4
2
+ . . . Vn
2
)/V1)
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through Vn are the amplitudes of the second
through nth harmonics. The THD calculated in this data
sheet uses all the harmonics up to the fi fth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0,
1, 2, 3, etc. The 3rd order intermodulation products are
2fa + fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodula-
tion distortion is defi ned as the ratio of the RMS value of
either input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced
by 3dB for a full scale input signal.
Aperture Delay Time
The time from when CLK reaches midsupply to the instant that
the input signal is held by the sample and hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion
to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNR
JITTER
= –20log (2π • f
IN
• t
JITTER
)
Crosstalk
Crosstalk is the coupling from one channel (being driven
by a full-scale signal) onto the other channel (being driven
by a –1dBFS signal).
CONVERTER OPERATION
As shown in Figure 1, the LTC2282 is a dual CMOS pipelined
multistep converter. The converter has six pipelined ADC
stages; a sampled analog input will result in a digitized
value fi ve cycles later (see the Timing Diagram section).
For optimal AC performance the analog inputs should be
driven differentially. For cost sensitive applications, the
LTC2282
12
2282fb
APPLICATIONS INFORMATION
analog inputs can be driven single-ended with slightly
worse harmonic distortion. The CLK input is single-ended.
The LTC2282 has two phases of operation, determined by
the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifi er.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplifi ed and
output by the residue amplifi er. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the Functional Block Diagram.
At the instant that CLK transitions from low to high, the
sampled input is held. While CLK is high, the held input
voltage is buffered by the S/H amplifi er which drives the
fi rst pipelined ADC stage. The fi rst stage acquires the
output of the S/H during this high phase of CLK. When
CLK goes back low, the fi rst stage produces its residue
which is acquired by the second stage. At the same
time, the input S/H goes back to acquiring the analog
input. When CLK goes back high, the second stage pro-
duces its residue which is acquired by the third stage.
An identical process is repeated for the third, fourth and
fi fth stages, resulting in a fi fth stage residue that is sent
to the sixth stage ADC for fi nal evaluation.
Each ADC stage following the fi rst has additional range to
accommodate fl ash and amplifi er offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2282 CMOS
differential sample-and-hold. The analog inputs are con-
nected to the sampling capacitors (C
SAMPLE
) through NMOS
transistors. The capacitors shown attached to each input
(C
PARASITIC
) are the summation of all other capacitance
associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage. When
CLK transitions from low to high, the sampled input voltage
is held on the sampling capacitors. During the hold phase
when CLK is high, the sampling capacitors are disconnected
from the input and the held voltage is passed to the ADC
core for processing. As CLK transitions from high to low,
the inputs are reconnected to the sampling capacitors to
V
DD
V
DD
V
DD
15Ω
15Ω
C
PARASITIC
1pF
C
PARASITIC
1pF
C
SAMPLE
4pF
C
SAMPLE
4pF
LTC2282
A
IN
+
A
IN
–
CLK
2282 F02
Figure 2. Equivalent Input Circuit
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LTC2282IUP#PBF

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Buy LTC2282IUP#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2x 12-B, 105Msps L Pwr 3V ADC
Lifecycle:
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