LTC2282IUP#PBF Datasheet LTC2282IUP#PBF, LTC2282IUP#TRPBF, LTC2282CUP | P16-P18

LTC2282

2282fb

APPLICATIONS INFORMATION

The noise performance of the LTC2282 can depend on the

clock signal quality as much as on the analog input. Any

noise present on the clock signal will result in additional

aperture jitter that will be RMS summed with the inherent

ADC aperture jitter.

In applications where jitter is critical, such as when digi-

tizing high input frequencies, use as large an amplitude

as possible. Also, if the ADC is clocked with a sinusoidal

signal, ﬁ lter the CLK signal to reduce wideband noise and

distortion products generated by the source.

It is recommended that CLKA and CLKB are shorted to-

gether and driven by the same clock source. If a small time

delay is desired between when the two channels sample

the analog inputs, CLKA and CLKB can be driven by two

different signals. If this delay exceeds 1ns, the performance

of the part may degrade. CLKA and CLKB should not be

driven by asynchronous signals.

Figures 12 and 13 show alternatives for converting a

differential clock to the single-ended CLK input. The use

of a transformer provides no incremental contribution

to phase noise. The LVDS or PECL to CMOS translators

provide little degradation below 70MHz, but at 140MHz will

degrade the SNR compared to the transformer solution.

The nature of the received signals also has a large bear-

ing on how much SNR degradation will be experienced.

For high crest factor signals such as WCDMA or OFDM,

where the nominal power level must be at least 6dB to

8dB below full scale, the use of these translators will have

a lesser impact.

The transformer in the example may be terminated with

the appropriate termination for the signaling in use. The

use of a transformer with a 1:4 impedance ratio may be

desirable in cases where lower voltage differential signals

are considered. The center tap may be bypassed to ground

through a capacitor close to the ADC if the differential

signals originate on a different plane. The use of a ca-

pacitor at the input may result in peaking, and depending

on transmission line length may require a 10Ω to 20Ω

ohm series resistor to act as both a low pass ﬁ lter for

high frequency noise that may be induced into the clock

line by neighboring digital signals, as well as a damping

mechanism for reﬂ ections.

Maximum and Minimum Conversion Rates

The maximum conversion rate for the LTC2282 is

105Msps. The lower limit of the LTC2282 sample rate is

determined by droop of the sample-and-hold circuits. The

pipelined architecture of this ADC relies on storing analog

CLK

50Ω

0.1μF

4.7μF

FERRITE

BEAD

CLEAN

SUPPLY

SINUSOIDAL

CLOCK

INPUT

2282 F11

NC7SVU04

LTC2282

Figure 11. Sinusoidal Single-Ended CLK Drive

CLK

100Ω

0.1μF

4.7μF

FERRITE

BEAD

CLEAN

SUPPLY

IF LVDS, USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

2282 F12

LTC2282

Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter

Figure 13. LVDS or PECL CLK Drive Using a Transformer

CLK

5pF-30pF

ETC1-1T

0.1μF

FERRITE

BEAD

DIFFERENTIAL

CLOCK

INPUT

2282 F13

LTC2282

2282fb

APPLICATIONS INFORMATION

signals on small valued capacitors. Junction leakage will

discharge the capacitors. The speciﬁ ed minimum operat-

ing frequency for the LTC2282 is 1Msps.

Clock Duty Cycle Stabilizer

An optional clock duty cycle stabilizer circuit ensures

high performance even if the input clock has a non

50% duty cycle. Using the clock duty cycle stabilizer is

recommended for most applications. To use the clock

duty cycle stabilizer, the MODE pin should be connected

to 1/3V

or 2/3V

using external resistors.

This circuit uses the rising edge of the CLK pin to sample

the analog input. The falling edge of CLK is ignored and

the internal falling edge is generated by a phase-locked

loop. The input clock duty cycle can vary from 40% to

60% and the clock duty cycle stabilizer will maintain a

constant 50% internal duty cycle. If the clock is turned off

for a long period of time, the duty cycle stabilizer circuit

will require a hundred clock cycles for the PLL to lock

onto the input clock.

For applications where the sample rate needs to be changed

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken to

make the sampling clock have a 50% (±5%) duty cycle.

DIGITAL OUTPUTS

Table 1 shows the relationship between the analog input

voltage, the digital data bits and the overﬂ ow bit.

Digital Output Buffers

Figure 14 shows an equivalent circuit for a single out-

put buffer. Each buffer is powered by OV

and OGND,

isolated from the ADC power and ground. The additional

N-channel transistor in the output driver allows opera-

tion down to low voltages. The internal resistor in series

with the output makes the output appear as 50Ω to ex-

ternal circuitry and may eliminate the need for external

damping resistors.

As with all high speed/high resolution converters, the

digital output loading can affect the performance. The

digital outputs of the LTC2282 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. For full speed

operation the capacitive load should be kept under 10pF.

Lower OV

voltages will also help reduce interference

from the digital outputs.

Data Format

Using the MODE pin, the LTC2282 parallel digital output

can be selected for offset binary or 2’s complement for-

mat. Connecting MODE to GND or 1/3V

selects offset

binary output format. Connecting MODE to 2/3V

selects 2’s complement output format. An external

resistor divider can be used to set the 1/3V

or 2/3V

logic values. Table 2 shows the logic states for the

MODE pin.

Table 1. Output Codes vs Input Voltage

– A

–

(2V Range) OF

D11 – D0

(Offset Binary)

D11 – D0

(2’s Complement)

>+1.000000V

+0.999512V

+0.999024V

1111 1111 1111

1111 1111 1110

0111 1111 1111

0111 1111 1110

+0.000488V

0.000000V

–0.000488V

–0.000976V

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

–0.999512V

–1.000000V

<–1.000000V

0000 0000 0001

0000 0000 0000

1000 0000 0001

1000 0000 0000

LTC2282

2282 F14

0.1μF

43Ω

TYPICAL

DATA

OUTPUT

OGND

0.5V

TO 3.6V

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 14. Digital Output Buffer

LTC2282

2282fb

APPLICATIONS INFORMATION

Table 2. MODE Pin Function

MODE Pin Output Format

Clock Duty

Cycle Stabilizer

0 Offset Binary Off

1/3V

Offset Binary On

2/3V

2’s Complement On

2’s Complement Off

Overﬂ ow Bit

When OF outputs a logic high the converter is either over-

ranged or underranged.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OV

, should be tied to the

same power supply as for the logic being driven. For example,

if the converter is driving a DSP powered by a 1.8V supply,

then OV

should be tied to that same 1.8V supply.

can be powered with any voltage from 500mV up to

3.6V. OGND can be powered with any voltage from GND

up to 1V and must be less than OV

. The logic outputs

will swing between OGND and OV

Output Enable

The outputs may be disabled with the output enable pin,

OE. OE high disables all data outputs including OF. The

data access and bus relinquish times are too slow to

allow the outputs to be enabled and disabled during full

speed operation. The output Hi-Z state is intended for use

during long periods of inactivity. Channels A and B have

independent output enable pins (OEA, OEB).

Sleep and Nap Modes

The converter may be placed in shutdown or nap modes

to conserve power. Connecting SHDN to GND results in

normal operation. Connecting SHDN to V

and OE to V

results in sleep mode, which powers down all circuitry,

including the reference, and typically dissipates 1mW.

When exiting sleep mode, it will take milliseconds for the

output data to become valid because the reference capaci-

tors have to recharge and stabilize. Connecting SHDN to

and OE to GND results in nap mode, which typically

dissipates 30mW. In nap mode, the on-chip reference circuit

is kept on, so that recovery from nap mode is faster than

that from sleep mode, typically taking 100 clock cycles. In

both sleep and nap modes, all digital outputs are disabled

and enter the Hi-Z state.

Channels A and B have independent SHDN pins (SHDNA,

SHDNB). Channel A is controlled by SHDNA and OEA, and

channel B is controlled by SHDNB and OEB. The nap, sleep

and output enable modes of the two channels are completely

independent, so it is possible to have one channel operating

while the other channel is in nap or sleep mode.

Digital Output Multiplexer

The digital outputs of the LTC2282 can be multiplexed onto

a single data bus if the sample rate is 80Msps, or less. The

MUX pin is a digital input that swaps the two data busses.

If MUX is high, channel A comes out on DA0-DA11, OFA;

channel B comes out on DB0-DB11, OFB. If MUX is low,

the output busses are swapped and channel A comes out

on DB0-DB11, OFB; channel B comes out on DA0-DA11,

OFA. To multiplex both channels onto a single output bus,

connect MUX, CLKA and CLKB together (see the Timing

Diagram for the multiplexed mode). The multiplexed data

is available on either data bus—the unused data bus can

be disabled with its OE pin.

Grounding and Bypassing

The LTC2282 requires a printed circuit board with a clean,

unbroken ground plane. A multilayer board with an internal

ground plane is recommended. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track or underneath the ADC.

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LTC2282IUP#PBF

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2x 12-B, 105Msps L Pwr 3V ADC

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LTC2282IUP#PBF

LTC2282IUP#PBF

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