LTC2282
13
2282fb
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small, the charging glitch seen at the input will
be small. If the input change is large, such as the change
seen with input frequencies near Nyquist, then a larger
charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, A
IN
+
should be driven with the input signal and A
IN
–
should be
connected to 1.5V or V
CM
.
Common Mode Bias
For optimal performance, the analog inputs should be
driven differentially. Each input should swing ±0.5V for the
2V range or ±0.25V for the 1V range, around a common
mode voltage of 1.5V. The V
CM
output pin may be used
to provide the common mode bias level. V
CM
can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The V
CM
pin must be bypassed to ground
close to the ADC with a 2.2μF, or greater, capacitor.
Input Drive Impedance
As with all high performance, high speed ADCs, the dy-
namic performance of the LTC2282 can be infl uenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and reactance can infl uence
SFDR. At the falling edge of CLK, the sample-and-hold
circuit will connect the 4pF sampling capacitor to the input
pin and start the sampling period. The sampling period
ends when CLK rises, holding the sampled input on the
sampling capacitor. Ideally the input circuitry should be fast
enough to fully charge the sampling capacitor during the
sampling period 1/(2F
ENCODE
); however, this is not always
possible and the incomplete settling may degrade the SFDR.
APPLICATIONS INFORMATION
The sampling glitch has been designed to be as linear as
possible to minimize the effects of incomplete settling.
For the best performance, it is recommended to have a
source impedance of 100Ω, or less, for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
Figure 3 shows the LTC2282 being driven by an RF trans-
former with a center tapped secondary. The secondary
center tap is DC biased with V
CM
, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
hold. Figure 3 shows a 1:1 turns ratio transformer. Other
turns ratios can be used if the source impedance seen
by the ADC does not exceed 100Ω for each ADC input.
A disadvantage of using a transformer is the loss of low
frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
Figure 4 demonstrates the use of a differential amplifi er to
convert a single-ended input signal into a differential input
signal. The advantage of this method is that it provides
low frequency input response; however, the limited gain
bandwidth of most op amps will limit the SFDR at high
input frequencies.
25Ω
25Ω
25Ω
25Ω
0.1μF
A
IN
+
A
IN
–
12pF
2.2μF
V
CM
LTC2282
ANALOG
INPUT
0.1μF T1
1:1
T1 = MA/COM ETC1-1T
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2282 F03
Figure 3. Single-Ended to Differential Conversion
Using a Transformer
