LTC2282
19
2282fb
APPLICATIONS INFORMATION
High quality ceramic bypass capacitors should be used
at the V
DD
, OV
DD
, V
CM
, REFH, and REFL pins. Bypass
capacitors must be located as close to the pins as pos-
sible. Of particular importance is the 0.1μF capacitor
between REFH and REFL. This capacitor should be placed
as close to the device as possible (1.5mm or less). A size
0402 ceramic capacitor is recommended. The large 2.2μF
capacitor between REFH and REFL can be somewhat
further away. The traces connecting the pins and bypass
capacitors must be kept short and should be made as
wide as possible.
The LTC2282 differential inputs should run parallel
and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2282 is transferred
from the die through the bottom-side exposed pad and
package leads onto the printed circuit board. For good
electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to
a ground plane of suffi cient area.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix
or Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable.
You must not allow the clock to overshoot the supplies or
performance will suffer. Do not fi lter the clock signal with
a narrow band fi lter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a fi lter
close to the ADC may be benefi cial. This fi lter should be
close to the ADC to both reduce roundtrip refl ection times,
as well as reduce the susceptibility of the traces between
the fi lter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the re-
timing fl ip-fl op as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated in
the waveguides that exist between the layers of multilayer
PCBs. The differential pairs must be close together, and
distanced from other signals. The differential pair should
be guarded on both sides with copper distanced at least
3
X the distance between the traces, and grounded with
vias no more than 1/4 inch apart.
