LTC2282
8
2282fb
PIN FUNCTIONS
A
INA
+
(Pin 1): Channel A Positive Differential Analog
Input.
A
INA
–
(Pin 2):
Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4):
Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
REFLA (Pins 5, 6):
Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1μF ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2μF ceramic chip capacitor
and to ground with a 1μF ceramic chip capacitor.
V
DD
(Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to
GND with 0.1μF ceramic chip capacitors.
CLKA (Pin 8):
Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9):
Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12):
Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2μF ceramic chip capaci-
tor and to ground with a 1μF ceramic chip capacitor.
REFHB (Pins 13, 14):
Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1μF ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2μF ceramic chip capaci-
tor and to ground with a 1μF ceramic chip capacitor.
A
INB
–
(Pin 15): Channel B Negative Differential Analog
Input.
A
INB
+
(Pin 16):
Channel B Positive Differential Analog
Input.
GND (Pins 17, 64):
ADC Power Ground.
SENSEB (Pin 19):
Channel B Reference Programming Pin.
Connecting SENSEB to V
CMB
selects the internal reference
and a ±0.5V input range. V
DD
selects the internal reference
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of ±V
SENSEB
. ±1V is the largest valid input range.
V
CMB
(Pin 20):
Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2μF ceramic chip
capacitor. Do not connect to V
CMA
.
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX is
high, channel A comes out on DA0-DA11, OFA; channel B
comes out on DB0-DB11, OFB. If MUX is low, the output
busses are swapped and channel A comes out on DB0-
DB11, OFB; channel B comes out on DA0-DA11, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together. (This is not recommended
at clock frequencies above 80Msps.)
SHDNB (Pin 22):
Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
DD
results in normal operation
with the outputs at high impedance. Connecting SHDNB
to V
DD
and OEB to GND results in nap mode with the
outputs at high impedance. Connecting SHDNB to V
DD
and OEB to V
DD
results in sleep mode with the outputs
at high impedance.
OEB (Pin 23):
Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42):
Do Not Connect These Pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39):
Channel B Digital
Outputs. DB11 is the MSB.
OGND (Pins 31, 50):
Output Driver Ground.
OV
DD
(Pins 32, 49):
Positive Supply for the Output Drivers.
Bypass to ground with a 0.1μF ceramic chip capacitor.
OFB (Pin 40):
Channel B Overfl ow/Underfl ow Output. High
when an overfl ow or underfl ow has occurred.
DA0 – DA11 (Pins 43 to 48, 51 to 56):
Channel A Digital
Outputs. DA11 is the MSB.
OFA (Pin 57):
Channel A Overfl ow/Underfl ow Output. High
when an overfl ow or underfl ow has occurred.
OEA (Pin 58):
Channel A Output Enable Pin. Refer to
SHDNA pin function.
