MT8952B Data Sheet
3
Zarlink Semiconductor Inc.
4 CDSTi C and D channel Input in ST-BUS format - This is the serial formatted data input to the
receiver in NRZ form. It must be in ST-BUS format if the Protocol Controller is in Internal
Timing Mode with the input data in selected timeslots (0,2,3 and 4) and the C-channel
information in timeslot No.1. If the Controller is in External Timing Mode, the serial input data
is sampled on the falling edge of the clock CKi when RxCEN
is LOW. If RxCEN is HIGH, the
clock to receive section is inhibited.
5WD
Watch-Dog Timer output - Normally a HIGH level output, going LOW if the Watchdog timer
times out or if the external reset (RST
) is held LOW. The WD output remains LOW as long
as RST
is held LOW.
6IRQ
Interrupt Request Output (Open Drain) - This active LOW output notifies the controlling
microprocessor of an interrupt request. It goes LOW only when the bits in the Interrupt
Enable Register are programmed to acknowledge the source of the interrupt as defined in
the Interrupt Flag Register.
7-10 A0-A3 Address Bus Inputs - These bits address the various registers in the Protocol Controller.
They select the internal registers in conjunction with CS
, R/W inputs and E Clock. (Refer to
Table 1.)
11 CS
Chip Select Input - This is an active LOW input enabling the Read or Write operation to
various registers in the Protocol Controller.
12 E Enable Clock Input - This input activates the Address Bus and R/W
input and enables data
transfers on the Data Bus.
13 R/W
Read/Write Control - This input controls the direction of data flow on the data bus. When
HIGH, the I/O buffer acts as an output driver and as an input buffer when LOW.
14 V
SS
Ground (0 Volt).
15-22 D0-D7 Bidirectional Data Bus - These Data Bus I/O ports allow the data transfer between the
HDLC Protocol Controller and the microprocessor.
23 REOP Receive End Of Packet (Output) - This is a HIGH going pulse that occurs for one bit
duration when a closing flag is detected on the incoming packets, or the incoming packet is
aborted, or when an invalid packet of 24 or more bits is received.
24 TEOP Transmit End Of Packet (Output) - This is a HIGH going pulse that occurs for one bit
duration when a packet is transmitted correctly or aborted.
25 CKi Clock Input (Bit rate clock or 2 x bit rate clock in ST-BUS format while in the Internal
Timing Mode and bit rate Clock in the External Timing Mode) - This is the clock input
used for shifting in/out the formatted packets. It can be at bit rate (C2i) or twice the bit rate
(C4i
) in ST-BUS format while the Protocol Controller is in the Internal Timing Mode. Whether
the clock should be C2i (typically 2.048 MHz) or C4i
(typically 4.096 MHz) is decided by the
BRCK bit in the Timing Control Register. If the Protocol Controller is in the External Timing
Mode, it is at the bit rate.
26 F0i
Frame Pulse Input - This is the frame pulse input in ST-BUS format to establish the
beginning of the frame in the Internal Timing Mode. This is also the signal clocking the
watchdog timer.
27 RST
RESET Input - This is an active LOW Schmitt Trigger input, resetting all the registers
including the transmit and receive FIFOs and the watchdog timer.
28 V
DD
Supply (5 Volts).
Pin Description (continued)
Pin No. Name Description
