MT8952B Data Sheet
25
Zarlink Semiconductor Inc.
Figure 20 - Watchdog Timer Input and Output
† Timing is over recommended temperature & power supply voltages (V
DD
=5V5%, V
SS
=0V, T
A
=–40 to 85C).
‡ Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 21 - RESET Timing
AC Electrical Characteristics
†
- Serial Port, RESET, WD Timer and IRQ Release Time (Figures 19, 20, 21 and
22). Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 Interrupt request release time t
IRQR
120 ns Test load circuit 2 (Fig.26)
2WD
output delay HIGH to LOW t
WDHL
135 ns Test load circuit 1 (Fig.26)
3WD
output delay LOW to HIGH t
WDLH
135 ns Test load circuit 1 (Fig.26)
4 TEOP/REOP output delay t
EOPD
110 ns Test load circuit 1 (Fig.26)
5 TEOP/REOP output hold time t
EOPH
110 ns Test load circuit 1 (Fig.26)
6 CDSTo delay from CKi t
STOD
125 ns Test load circuit 1 (Fig.26)
7 CDSTi setup time t
STiS
20 ns
8CDSTi hold time t
STiH
65 ns
9 RESET pulse width t
RST
100 ns
