MT8952B Data Sheet
28
Zarlink Semiconductor Inc.
† Timing is over recommended temperature & power supply voltages (V
DD
=5V5%, V
SS
=0V, T
A
=–40 to 85C).
‡ Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 25 - Serial Port Input and Output in ST-BUS Format (Internal Timing Mode)
Note: 1. Channels 0 to 4 can only be active on CDSTi and CDSTo in the Internal Timing Mode.
2. Clock input CKi can be either of the ST-BUS clocks C2i (2.048MHz) or C4i
(4.096 MHz) in the Internal Timing Mode.
3. The Frame Pulse set up and hold time measurements are to be referenced from the falling edge of C4i
or the rising edge of C2i depending on
the clock selected.
Figure 26 - Test Load Circuits
Note: Active Low to High impedance times are measured from the disabling signal edge to the time when V
out
has increased by 0.5 volts. Active High to
High impedance times are measured from the disabling signal edge to the time when V
out
has decreased by 0.5 volts.
6 CDSTi hold time t
STiH
65 ns
7 C2i clock period
t
C2i
400 ns
8C4i
clock period t
C4i
200 ns
AC Electrical Characteristics
†
- Serial Port in Internal Timing Mode - (Figure 25)
Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
F0i
CKi
(C4i
)
CKi
(C2i)
CDSTo
CDSTi
t
F0iW
t
F0iH
t
C4i
t
F0iS
t
C2i
t
SToZL
t
SToZH
HIGH IMPEDANCE
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
t
STiH
t
STiS
Ch. 31
Bit 0
Ch. 0
Bit 7
Ch. 0
Bit 6
Ch. 0
Bit 5
From
output
under test
Test
point
C
L
Test load circuit- 1
V
DD
R
L
=1k
Test
point
From
output
under test
Test load circuit- 2 Test load circuit - 3
From
output
under test
C
L
C
L
Test
point
S
1
V
DD
V
SS
R
L
=1k
Note: S
1
is in position A
when measuring t
PLZ
and in position B when
measuring t
PHZ
. See
note below.
C
L
=
200 pF for
on Data Bus
150 pF for
measurements
on CDSTo
50 pF for
others
measurements
A
B
