MT8952B Data Sheet
11
Zarlink Semiconductor Inc.
FA - Frame Abort: When set HIGH, this bit’tags’ the next byte written to the transmit FIFO and causes an abort
sequence (eight ONEs) to be transmitted when it reaches the bottom of the FIFO. The abort sequence will be
transmitted instead of the byte that was tagged. The FA bit is cleared to ZERO upon writing the data to the transmit
FIFO. As a result, a ‘read’ of this register bit will not reflect the last data written to it.
EOP - End Of Packet: Writing a ONE to this bit ‘tags’ the next byte written to the transmit FIFO to indicate that it is
the last data byte of the packet. This bit is cleared to ZERO upon writing the data to the transmit FIFO. As a result,
a read of this register bit will not indicate the last data written to it.
Receive Address Register (Read/Write)
Figure 8 - Receive Address Register
The data in this register (Figure 8) defines the unique address for the HDLC Protocol Controller. If address
recognition is enabled using the RxAD and RA6/7 bits in the Control Register, an incoming packet is recognized
only if its address byte (seven or six most significant bits) matches the corresponding bits in this register or if the
address is an "all-call". The LSB of the Receiver Address Register is set LOW permanently and the address
comparison is done only on remaining bits of the register.
C-Channel Control Register (Read/Write)
Figure 9 - C-Channel Control Register
The data written to this register (Figure 9) is transmitted on channel-1 slot of the outgoing ST-BUS (CDSTo), when
enabled by C1EN bit in the Timing Control Register. This feature can only be used when the HDLC Protocol
Controller is in the Internal Timing Mode.
Timing Control Register (Read/Write)
The Timing Control Register (Figure 10) controls the timing mode and other related operations and provides a
software reset to the Protocol Controller. The various bits in this register are described below:
Figure 10 - Timing Control Register
RST - Reset: When this bit is set HIGH, all the registers in the HDLC Protocol Controller are reset and the data in
the FIFOs is lost. This is equivalent to the external reset with the exception that the RST bit does not affect itself or
the Watchdog Timer Register and WD
output. The RST bit must be “cleared” (written as a logic “0”) twice before the
MT8952B will be removed from its reset state (see section on RESET operation).
IC - Internal Control: When this bit is cleared to ZERO, the Protocol Controller is in the External Timing Mode.
The transmit and receive sections are enabled by the inputs TxCEN
and RxCEN respectively, and F0i is used only
for the watchdog timer operation. When this bit is a ONE, the Protocol Controller is in the Internal Timing Mode. The
transmit and receive sections are enabled by the internally generated timings derived from the inputs CKi and F0i
.
The F0i
input defines the beginning of a frame (Figure 24) and the transmitter and receiver sections are enabled in
the timeslots as determined by the bits TCO-TC3. The inputs TxCEN
and RxCEN are ignored in this mode.
D7 D6 D5 D4 D3 D2 D1 D0
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
D7 D6 D5 D4 D3 D2 D1 D0
CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0
D7 D6 D5 D4 D3 D2 D1 D0
RST IC C1EN BRCK TC3 TC2 TC1 TC0
