MT8952B Data Sheet
22
Zarlink Semiconductor Inc.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
* Outputs unloaded. Input pins 12 and 25 clocked at 2048 kHz. All other inputs at V
SS
.
Timing is over recommended temperature & power supply voltages (V
DD
=5V5%, V
SS
=0V, T
A
=–40 to 85C).
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
10 O
U
T
P
U
T
Output HIGH current (on all
the outputs except IRQ
)
I
OH
-5 -16 mA V
OH
=2.4 V
11 Output LOW current (on all
the outputs including IRQ
)
I
OL
510 mAV
OL
=0.4 V
12 Output capacitance C
o
15 pF
AC Electrical Characteristics
- Microprocessor Interface - (Figures 17 and 18)
Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym. Min. Typ.
Max. Units Test Conditions
1 Delay between CS
and E clock t
CSE
0ns
2 Cycle time t
CYC
205 ns
3 E Clock pulse width HIGH t
EWH
145 ns
4 E Clock pulse width LOW t
EWL
60 ns
5 Read/Write setup time t
RWS
20 ns
6 Read/Write hold time t
RWH
10 ns
7 Address setup time t
AS
20 ns
8 Address hold time t
AH
60 ns
9 Data setup time (write) t
DSW
35 ns
10 Data hold time (write) t
DHW
10 ns
11 E clock to valid data delay t
DZL
t
DZH
145
ns
Test load circuit 1 (Fig. 26)
C
L
=200pF
12 Data hold time (read) t
DLZ
t
DHZ
10 60
ns Test load circuit 3 (Fig. 26)
DC Electrical Characteristics -
Voltages are with respect to ground (VSS) unless otherwise stated.
V
DD
=5V5%, V
SS
=0V, T
A
=-40 to 85C.
Characteristics Sym. Min. Typ.
Max. Units Test Conditions
MT8952B Data Sheet
23
Zarlink Semiconductor Inc.
Figure 17 - Timing Information for MPU Write
CS
E
CS
E
R/W
A0-A3
D0-D7
NOTE: The write cycle can be initiated either by the falling edge of CS
or the rising edge of E clock whichever occurs last. Similarly
the cycle can be terminated by CS
(rising edge) or E clock (falling edge) whichever occurs first. The timing relations are to be
referenced from the active edge initiating or terminating the cycle
t
CSE
t
EWH
t
EWL
t
r
t
f
t
CYC
t
CSE
t
RWS
t
RWH
t
AS
t
AH
t
DSW
t
DHW
E clock initiates and
terminates the write cycle
CS
initiates and
terminates the write cycle
MT8952B Data Sheet
24
Zarlink Semiconductor Inc.
Figure 18 - Timing Information for MPU Read
Figure 19 - Interrupt Request Release Time
CS
E
CS
E
R/W
A0-A3
D0-D7
E clock initiates and
terminates the read cycle
CS
initiates and
terminates the read cycle
VALID DATA
High Impedance
High Impedance
t
CSE
t
EWH
t
r
t
f
t
CYC
t
CSE
t
RWS
t
RWH
t
AS
t
AH
t
DZL
t
DZH
t
DLZ
t
DHZ
t
EWL
NOTE: The read cycle can be initiated either by the falling edge of CS or the rising edge of E clock whichever occurs last. Similarly
the cycle can be terminated by CS
(rising edge) or E clock (falling edge) whichever occurs first. The timing relations are to be
referenced from the active edge initiating or terminating the cycle.
E
IRQ
t
IRQR

MT8952BS1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free HDLC PROTOCOL CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet