MT8952BS1 Datasheet MT8952BS1, MT8952BP1, MT8952BPR1 | P13-P15

MT8952B Data Sheet

Zarlink Semiconductor Inc.

Tx 4/19 FULL - Transmit FIFO 4/19 full: This bit if set HIGH, indicates that the transmit FIFO has only 4 bytes

remaining in it and another 15 bytes could be loaded. This bit has significance only when the transmit FIFO is being

depleted and not when it is getting loaded.

Tx URUN - Transmit FIFO underrun: This bit when HIGH, identifies that the transmit FIFO is empty without the

Protocol Controller being given the ‘end of packet’ indication. This indicates that the transmit FIFO has underrun

and the Protocol Controller will transmit an abort sequence automatically. Tx DONE will be set 8 bit times after Tx

URUN is set.

Rx15/19 FULL - Receive FIFO 15/19 full: This bit when HIGH, confirms that the receive FIFO has 15 bytes in it

and it can receive four more bytes.

Rx OFLW - Receive FIFO overflow: This bit when set HIGH, indicates that the receive FIFO is full and a ‘write’

occurred indicating an overflow. The byte causing this and all the subsequent bytes written while the FIFO is in this

state are lost. The receiver begins to search for a new start flag.

Watchdog Timer Register (Write)

The Watchdog Timer Register operates in conjunction with the Watchdog Timer and the WD

output. Writing the

code of XXX0 1010 in the register resets the WD timer. If the register is not re-written within 2

cycles of F0i after

resetting the timer, the WD

output goes LOW. This register serves the sole purpose of resetting the timer and hence

relevant only if it is written with the above data.

Interrupt Enable Register (Read/Write)

This register enables/disables the interrupts as specified in the Interrupt Flag Register (IFR). Setting HIGH the

appropriate bits in this register (IER) enables the associated interrupt source. However, the masked bits in the IFR

are still valid but they do not cause the IRQ

output to go LOW. The description of the bits enabling the various

interrupts is identical to those of the Interrupt Flag Register.

General Status Register (Read)

This register (Figure 12) contains the general status information on the Protocol Controller.

Figure 12 - General Status Register

Rx OFLW - Receive FIFO overflow: This bit, if set HIGH, indicates that the receive FIFO has overflowed. The byte

causing this and all the subsequent bytes written while the FIFO is in this state are lost. Note that this bit is the

same as the Rx OFLW bit in Interrupt Flag Register (IFR) and can only be cleared by reading the IFR.

Tx URUN - Transmit FIFO Underrun: When HIGH, this bit indicates that the transmit FIFO has underrun. Under

this condition the packet being transmitted is aborted. This bit is the same as the Tx URUN bit in the Interrupt Flag

GA - Go Ahead: This bit is set HIGH if a ‘go ahead’ is received on the incoming data stream and is cleared when

the Interrupt Flag Register is read. This bit is the same as the GA bit in the IFR.

ABRT - Abort: The reception of contiguous seven ONEs on incoming data, sets this bit HIGH and reading the

General Status Register, clears it.

IRQ - Interrupt Request: This bit refers to the status of the interrupt request output from the Protocol Controller. If

HIGH, it indicates that the IRQ

(pin 6) output is LOW and vice versa.

IDLE - Idle Channel: This bit, if set HIGH, identifies that the receiver is detecting an idle channel at its input

(minimum 15 ONEs).

D7 D6 D5 D4 D3 D2 D1 D0

OFLW

URUN

GA ABRT IRQ IDLE LOW HIGH

MT8952B Data Sheet

Zarlink Semiconductor Inc.

C-Channel Status Register (Read)

Figure 13 - C-Channel Status Register

The C-Channel Register (Figure 13) continuously stores the data received during the channel-1 timeslot of the

incoming ST-BUS (CDSTi) during the Internal Timing Mode of the Protocol Controller.

Reset

When the MT8952B is reset by a low going pulse on the RST pin or by setting (logic high) the RST bit in the Timing

Control Register, the device is put into the following state:

a. All bits in the Timing Control Register are cleared (logic 0) by an external reset. An internal reset clears all

bits except the RST bit.

b. All bits in the Interrupt Enable Register are cleared (logic 0).

c. All bits in the Control Register are cleared (logic 0).

d. All bits in the Interrupt Register are cleared (logic 0).

e. All bits in the General Status Register are cleared (logic 0) except for the two least significant bits.

f. Receive and Transmit Registers are cleared and the FIFO Status Register reflects their state accordingly.

g. The WD

output is reset low by an external reset but is not affected by an internal reset.

h. The Transmitter and the Receiver are disabled.

Transmit Operation

After a reset, which the external circuitry should provide upon power up, the transmit section is disabled. Before

enabling this section, the timing should be set up. On reset, the serial port is set to External Timing Mode. In case

this is not desired, the Timing Control Register should be written to with the appropriate data. Once in the correct

timing mode, the Transmit Enable (TxEN) bit in the Control Register can be set. Now that the transmitter is enabled

it will be in the Idle channel state. If any other channel state or the transparent data transfer facility is required, the

IFTF bits in the Control Register should be set accordingly.

Normal Packets

To start a packet, the data is written into the transmit FIFO starting with the address field. All the data must be

written to the FIFO in a bytewide manner. When the data is detected in the transmit FIFO, the protocol controller will

proceed in one of the following ways:

If the transmitter is in idle state, the present byte of eight ONEs being transmitted is completed and then followed

by a start flag and subsequently the data in the transmit FIFO is transmitted.

If the transmitter is in the interframe time fill state, the flag presently being transmitted is finished and then another

start flag is transmitted before transmitting the data from the transmit FIFO.

If the transmitter is in go ahead state, it continues to be in that state even after the data is loaded into the FIFO. Only

when the IFTF bits are set to choose something other than go ahead will the data be transmitted.

If the transmitter is in transparent data transfer state, the protocol functions are disabled and the data in the transmit

FIFO is transmitted on CDSTo.

D7 D6 D5 D4 D3 D2 D1 D0

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

MT8952B Data Sheet

Zarlink Semiconductor Inc.

To indicate that the particular byte is the last byte of the packet, the EOP bit in the Control Register must be set

before the last byte is written into the transmit FIFO. The EOP bit is cleared automatically when the data byte is

written to the FIFO. After the transmission of the last byte in the packet, the frame check sequence (16 bits) is sent

followed by a closing flag. If there is any more data in the transmit FIFO, another flag is transmitted followed by the

new data. In case of no data in the FIFO, the transmitter assumes the selected link channel state. During the

transmission of either the data or the frame check sequence, the Protocol Controller checks the transmitted

information on a bit by bit basis and inserts a ZERO after every sequence of five consecutive ONEs.

Transmit FIFO Full

When the Transmit FIFO is full, this state is indicated by the Transmit FIFO status bits in the FIFO Status Register.

These bits do not change state for two bit periods after an access of the FIFO from either the serial port or the

microprocessor port. The bit period is determined by the CKi signal frequency. If the bus cycle of the controlling

microprocessor is much shorter than the bit period, the Transmit FIFO status bits may not be updated in time for the

next microprocessor read of the FIFO Status Register.

To make sure that the microprocessor does not overwrite the Tx FIFO, if over four bytes of information have been

written to the Tx FIFO, the microprocessor should wait for a 4/19 FULL interrupt before writing to the Tx FIFO again.

When a 4/19 FULL interrupt has been received, a maximum of 15 bytes should be written to the Tx FIFO, then

transfer of information to the Tx FIFO should stop and the 4/19 FULL interrupt should be waited for once more. The

FIFO may be allowed to empty if no more information is to be sent at the moment. This procedure should keep

software independent of the frequency of the CKi signal.

Transmit Underrun

A transmit underrun occurs when the last byte loaded into the transmit FIFO was not ‘flagged’ with the ‘end of

packet’ (EOP) bit and there are no more bytes in the FIFO. In such a situation, the Protocol Controller transmits the

abort sequence (eight ONEs) and moves to the selected link channel state.

Abort Transmission

If it is desired to abort the packet currently being loaded into the transmit FIFO, the next byte written to the FIFO

should be ‘flagged’ to cause this to happen. The FA bit of the Control Register must be set HIGH, before writing the

next byte into the FIFO. This bit is cleared automatically once the byte is written to the FIFO. When the ‘flagged’

byte reaches the bottom of the FIFO, a frame abort sequence is sent instead of the byte and the transmitter

operation returns to normal.

Go Ahead Transmission

By setting the IFTF bits in the Control Register appropriately the transmitter can be made to send the Go Ahead

sequences when the Protocol Controller is not sending the packets. Since the go ahead is defined as 011111110,

contiguous 7F

Hex

’

s appear as go aheads. As long as the IFTF bits are set to choose go aheads, the transmitter will

send them even if data is subsequently loaded into the FIFO. Only when the IFTF bits are set to select something

other than go aheads, will the data be transmitted.

C-Channel Transmission

By setting the C1EN bit in the Timing Control Register HIGH, the information loaded in the C-Channel Control

the Internal Timing Mode of the Protocol Controller.

Transparent Data Transfer

The IFTF bits in the Control Register can be set to provide transparent data transfer disabling the protocol

functions. The transmitter no longer generates the Flag, GA, Abort and Idle sequences nor does it insert the zeros

and calculate the FCS. It operates in both timing modes in bytewide manner and transmits data serially on CDSTo.

If the Protocol Controller is in the Internal Timing Mode and the Timing Control bits are set to select 2, 6 or 7

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MT8952BS1

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Manufacturer:

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Description:

Telecom Interface ICs Pb Free HDLC PROTOCOL CONTROLLER

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MT8952BS1

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