MT8952B Data Sheet
19
Zarlink Semiconductor Inc.
Figure 15 - HDLC Protocol Controller at the Primary End of the Link
Figure 16 - HDLC Protocol Controller at the Secondary End of the Link
M
I
C
R
O
P
R
O
C
E
S
S
O
R
D0-D7
R/W
CS
E
A0-A3
WD
RST
IRQ
CDSTo
CDSTi
DSTi
DSTo
C4
F0
MS0
0
MS1
0
MS2
0
B-CHANNELS (2 X 64 kbits/sec Max)
MT8952B
HDLC PROTOCOL
CONTROLLER
MT8972
DIGITAL
NETWORK
INTERFACE
CIRCUIT
F0i
CKi
TO
TWISTED
WIRE PAIR
(160 kbits/sec)
Primary Terminal End
Network Interface
Network
M
I
C
R
O
P
R
O
C
E
S
S
O
R
D0-D7
R/W
CS
E
A0-A3
WD
RST
IRQ
CDSTo
CDSTi
DSTi
DSTo
C4
F0
MS0
0
MS1
0
MS2
1
F0i
CKi
B-CHANNELS (2 X 64 kbits/sec Max)
MT8952B
HDLC PROTOCOL
CONTROLLER
MT8972
DIGITAL
NETWORK
INTERFACE
CIRCUIT
TO
TWISTED
WIRE PAIR
(160 kbits/sec)
Secondary Terminal End
Network Interface
Network
MT8952B Data Sheet
20
Zarlink Semiconductor Inc.
Primary End of the Link
The MT8952B is operating in the internal timing mode with the C-channel transceiver action enabled. The
processor loads the data or control information (D Channel) in the transmit FIFO which is packetized in HDLC
format and shifted out serially during the selected channels of the outgoing ST-BUS (CDSTo). The channels and
the number of bits per frame (frame period=125sec) can be selected by TC0-TC3 bits in the Timing Control
Register. Since channel 1 is reserved for the C-channel information and channels 2 and 3 carry B-channels (64
kbps each), the D-channel information can only be sent on channel-0. Similarly the incoming packets on CDSTi are
loaded into receive FIFO after the removal of all overhead bits and checked for any errors. The microprocessor will
then read the data from the receive FIFO.
The DNIC (MT8972) is selected to operate in single port, master mode with the digital network (DN) option enabled.
The B-channels, B1 and B2, are shown connected directly to the DNIC. Hence, these should be in ST-BUS format
enabled at the appropriate timeslot (channels 2 and 3). It can be the outputs of voice codecs (MT896X) providing
voice communication or data codecs (MT8950) for communication between RS232-C type terminals. It is possible
to use the HDLC protocol on B1 and B2 channels to provide the error detection.
This can be done by using a separate MT8952B enabled appropriately to shift out the formatted data during
channels 2 and 3 or by multiplexing the same MT8952B between B- and D- channels.
Secondary End of the Link
At the secondary end of the communication link, a similar procedure is adopted to transmit/receive the data and
control information.
The MT8952B operates in the Internal Timing Mode as at the primary end, but the DNIC (MT8972) is selected to
operate in single port, slave mode with the digital network capability enabled.
The other functions and procedures are similar to those at the primary end.
The timing signals like CKi (C2i or C4i
) and F0i are provided externally at the primary end and at the secondary
end, they are derived from the received data.
Although this application describes the communication between two stations over a dedicated link, it can
be modified to serve a switched communication path by additional control functions and a call set-up procedure
many of which can be achieved in software.
MT8952B Data Sheet
21
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
Absolute Maximum Ratings*
Parameter Symbol Min. Max. Units
1 Supply voltage V
DD
-0.3 7.0 V
2 Voltage on any pin (other than supply pins) V
I
V
SS
-0.3 V
DD
+0.3 V
3 Current on any pin (other than supply pins) I
I
/ I
O
25 mA
4 DC Supply or ground current I
DD
/ I
SS
50 mA
5 Storage temperature T
ST
-65 150 C
6 Package power dissipation Plastic P
D
0.6 W
Recommended Operating Conditions
- Voltages are with respect to ground (V
SS
) unless otherwise stated.
Characteristics Sym. Min. Typ.
Max. Units Test Conditions
1 Supply Voltage V
DD
4.75 5.0 5.25 V
2 Input HIGH voltage V
IH
2.4 V
DD
V For a Noise Margin of 400
mV
3 Input LOW voltage V
IL
V
SS
0.4 V For a Noise Margin of 400
mV
4 Frequency of operation f
CL
5.0 MHz When clock input is at twice
the bit rate.
5 Operating temperature T
A
-40 25 85 C
DC Electrical Characteristics -
Voltages are with respect to ground (VSS) unless otherwise stated.
V
DD
=5V5%, V
SS
=0V, T
A
=-40 to 85C.
Characteristics Sym. Min. Typ.
Max. Units Test Conditions
1 Supply Current (Quiescent) I
DD
110A Outputs unloaded and
clock input (CKi) grounded
2 Supply current (Operational) I
DD
0.4 1.0 mA *See below
3
I
N
P
U
T
Input HIGH voltage V
IH
2.0 V
4 Input LOW voltage V
IL
0.8 V
5 Input leakage current I
IZ
10 A
6 Input capacitance C
in
10 pF
7 HIGH switching point for
Schmitt Trigger (RST
) input
V
T+
4.0 V
8 LOW switching point for
Schmitt Trigger (RST
) input
V
T-
1.0 V
9 Hysteresis on Schmitt Trigger
(RST
) input
V
H
0.5 V

MT8952BS1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free HDLC PROTOCOL CONTROLLER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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