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ISL98001CQZ-210

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
10
FN6148.5
September 21, 2010
Pin Descriptions
SYMBOL MQFP PIN #(s) DESCRIPTION
R
IN
1 7 Analog input. Red Channel 1. DC couple or AC couple through 0.1µF.
G
IN
1 12 Analog input. Green Channel 1. DC couple or AC couple through 0.1µF.
B
IN
1 19 Analog input. Blue Channel 1. DC couple or AC couple through 0.1µF.
RGB
GND
1 13 Analog input. Ground reference for the R, G, and B inputs of channel 1 in the DC coupled configuration.
Connect to the same ground as Channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
1 14 Analog input. Sync on Green. Connect to G
IN
1 through a 0.01µF capacitor in series with a 500Ω resistor.
HSYNC
IN
1 33 Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND
A
. Connect to Channel 1's HSYNC
signal through a 680Ω series resistor.
VSYNC
IN
1 44 Digital input, 5V tolerant, 500mV hysteresis. Connect to Channel 1's VSYNC signal.
R
IN
2 22 Analog input. Red Channel 2. DC couple or AC couple through 0.1µF.
G
IN
2 24 Analog input. Green Channel 2. DC couple or AC couple through 0.1µF.
B
IN
2 28 Analog input. Blue Channel 2. DC couple or AC couple through 0.1µF.
RGB
GND
2 25 Analog input. Ground reference for the R, G, and B inputs of Channel 2 in the DC coupled configuration.
Connect to the same ground as Channel 1's R, G, and B termination resistors. This signal is not used in the
AC-coupled configuration, but the pin should still be tied to GND
A
.
SOG
IN
2 26 Analog input. Sync on Green. Connect to G
IN
1 through a 0.01µF capacitor in series with a 500Ω resistor.
HSYNC
IN
2 34 Digital input, 5V tolerant, 240mV hysteresis, 1.2kΩ impedance to GND
A
. Connect to Channel 2's HSYNC
signal through a 680Ω series resistor.
VSYNC
IN
2 45 Digital input, 5V tolerant, 500mV hysteresis. Connect to Channel 2's VSYNC signal.
CLOCKINV
IN
41 Digital input, 5V tolerant. When high, changes the pixel sampling phase by 180°. Toggle at frame rate during
VSYNC to allow 2x undersampling to sample odd and even pixels on sequential frames. Tie to D
GND
if
unused.
RESET
46 Digital input, 5V tolerant, active low, 70kΩ pullup to V
D
. Take low for at least 1µs and then high again to reset
the ISL98001. This pin is not necessary for normal use and may be tied directly to the V
D
supply.
XTAL
IN
39 Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XTAL
OUT
40 Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (See crystal spec for
recommended loading). Typical oscillation amplitude is 1.0V
P-P
centered around 0.5V.
XCLK
OUT
47 3.3V digital output. Buffered crystal clock output at f
XTAL
or f
XTAL
/2. May be used as system clock for other
system components.
SADDR 48 Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.
SCL 50 Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA 49 Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
R
P
[7:0] 112-119 3.3V digital output. Red channel, primary pixel data. 56k pulldown when three-stated.
R
S
[7:0] 100-107 3.3V digital output. Red channel, secondary pixel data. 56k pulldown when three-stated.
G
P
[7:0] 90-97 3.3V digital output. Green channel, primary pixel data. 56k pulldown when three-stated.
G
S
[7:0] 80-87 3.3V digital output. Green channel, secondary pixel data. 56k pulldown when three-stated.
B
P
[7:0] 68-75 3.3V digital output. Blue channel, primary pixel data. 56k pulldown when three-stated.
B
S
[7:0] 55-62 3.3V digital output. Blue channel, secondary pixel data. 56k pulldown when three-stated.
DATACLK 121 3.3V digital output. Data clock output. Equal to pixel clock rate in 24-bit mode, one half of pixel clock rate in
48-bit mode.
DATACLK 122 3.3V digital output. Inverse of DATACLK.
HS
OUT
125 3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals).
ISL98001
11
FN6148.5
September 21, 2010
VS
OUT
126 3.3V digital output. Artificial VSYNC output aligned with pixel data. VS
OUT
is generated 8 pixel clocks after
the trailing edge of HS
OUT
. This signal is usually not needed.
HSYNC
OUT
127 3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC
period. This output will pass composite sync signals and Macrovision signals if present on HSYNC
IN
or
SOG
IN
.
VSYNC
OUT
128 3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
V
A
6, 11, 18, 20, 29,
35
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
A
with 0.1µF.
GND
A
3, 5, 8, 10, 15,
17, 21, 23, 27,
30, 36
Ground return for V
A
and V
BYPASS
.
V
D
54, 67, 77, 89,
99, 111, 124
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
D
with 0.1µF.
GND
D
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
120, 123
Ground return for V
D
, V
CORE
, V
COREADC
, and V
PLL
.
V
X
38 Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
X
with 0.1µF.
GND
X
37 Ground return for V
X
.
V
BYPASS
4, 9, 16 Bypass these pins to GND
A
with 0.1µF. Do not connect these pins to each other or anything else.
VREG
IN
65 3.3V input voltage for V
CORE
voltage regulator. Connect to a 3.3V source and bypass to GND
D
with 0.1µF.
VREG
OUT
64 Regulated output voltage for V
PLL
, V
COREADC
and V
CORE
; typically 1.9V. Connect only to V
PLL
,
V
COREADC
and V
CORE
and bypass at input pins as instructed in the following. Do not connect to anything
else - this output can only supply power to V
PLL
, V
COREADC
and V
CORE
.
V
COREADC
31 Internal power for the ADC’s digital logic. Connect to VREG
OUT
through a 10Ω resistor and bypass to GND
D
with 0.1µF.
V
PLL
42 Internal power for the PLL’s digital logic. Connect to VREG
OUT
through a 10Ω resistor and bypass to GND
D
with 0.1µF.
V
CORE
52, 79, 109 Internal power for core logic. Connect to VREG
OUT
and bypass each pin to GND
D
with 0.1µF.
NC 1, 2, 63 Reserved. Do not connect anything to these pins.
Pin Descriptions (Continued)
SYMBOL MQFP PIN #(s) DESCRIPTION
ISL98001
12
FN6148.5
September 21, 2010
Register Listing
ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION
0x00 Device ID
(read only)
3:0 Device Revision 1 = initial silicon, 2 = second revision, etc.
7:4 Device ID 1 = ISL98001
0x01 SYNC Status
(read only)
0 HSYNC1 Active 0: HSYNC1 is Inactive
1: HSYNC1 is Active
1 HSYNC2 Active 0: HSYNC2 is Inactive
1: HSYNC2 is Active
2 VSYNC1 Active 0: VSYNC1 is Inactive
1: VSYNC1 is Active
3 VSYNC2 Active 0: VSYNC2 is Inactive
1: VSYNC2 is Active
4 SOG1 Active 0: SOG1 is Inactive
1: SOG1 is Active
5 SOG2 Active 0: SOG2 is Inactive
1: SOG2 is Active
6 PLL Locked 0: PLL is unlocked
1: PLL is locked to incoming HSYNC
7 CSYNC Detect at
Sync Splitter
0: Composite Sync signal not detected
1: Composite Sync signal is detected
0x02 SYNC Polarity
(read only)
0HSYNC1
Polarity
0: HSYNC1 is Active High
1: HSYNC1 is Active Low
1HSYNC2
Polarity
0: HSYNC2 is Active High
1: HSYNC2 is Active Low
2 VSYNC1
Polarity
0: VSYNC1 is Active High
1: VSYNC1 is Active Low
3 VSYNC2
Polarity
0: VSYNC2 is Active High
1: VSYNC2 is Active Low
4HSYNC1
Trilevel
0: HSYNC1 is Standard Sync
1: HSYNC1 is Trilevel Sync
5HSYNC2
Trilevel
0: HSYNC2 is Standard Sync
1: HSYNC2 is Trilevel Sync
7:6 N/A Returns 0
0x03 HSYNC Slicer (0x33) 2:0 HSYNC1 Threshold 000 = lowest (0.4V) All values referred to
011 = default (1.6V) voltage at HSYNC input
111 = highest (3.2V) pin, 240mV hysteresis
3 Reserved Set to 00
6:4 HSYNC2 Threshold See HSYNC1
7 Disable Glitch Filter 0: HSYNC/VSYNC Glitch Filter Enabled (default)
1: HSYNC/VSYNC Glitch Filter Disabled
0x04 SOG Slicer (0x16)
Note: Due to normal device-to-device
variation in slicer levels, SOG Slicer settings
of 0 (0mV), 1 (20mV), and 2 (40mV) may not
be functional. The minimum recommended
SOG Slicer setting is 3 (60mV).
3:0 SOG1 and SOG2
Threshold
0x0 = lowest (0mV)
0x6 = default (120mV) 20mV step size
0xF = highest (300mV)
4 SOG Filter
Enable
0: SOG low pass filter disabled
1: SOG low pass filter enabled, 14MHz corner
(default)
5 SOG Hysteresis
Disable
0: 40mV SOG hysteresis enabled
1: 40mV SOG hysteresis disabled (default)
7:6 Reserved Set to 00.
ISL98001
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ISL98001CQZ-210

Mfr. #:
Buy ISL98001CQZ-210
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98001CQZ TRPL VID DIGIZER W/DIGTL PLL
Lifecycle:
New from this manufacturer.
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