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ISL98001CQZ-210

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
25
FN6148.5
September 21, 2010
may be significantly smaller, sometimes 300mV
P-P
or less.
In these cases the sync slicer will continue to operate
correctly, but the TriLevel Detect bit may not be set. Trilevel
detection accuracy can be enhanced by polling the trilevel
bit multiple times. If HSYNC is inactive, SOG is present, and
the TriLevel Sync Detect bit is read as a 1, there is a high
likelihood there is trilevel sync.
CSYNC Present
If a composite sync source (either CSYNC on HSYNC or
SOG) is selected through bits 3 and 4 of register 0x05, the
CSYNC Present bit in register 0x01 should be set. CSYNC
Present detects the presence of a low frequency, repetitive
signal inside HSYNC, which indicates a VSYNC signal. The
CSYNC Present bit should be used to confirm that the signal
being received is a reliable composite sync source.
SYNC Output Signals
The ISL98001 has 2 pairs of HSYNC and VSYNC output
signals, HSYNC
OUT
and VSYNC
OUT
, and HS
OUT
and
VS
OUT
.
HSYNC
OUT
and VSYNC
OUT
are buffered versions of the
incoming sync signals; no synchronization is done. These
signals are used for mode detection
HS
OUT
and VS
OUT
are generated by the ISL98001’s logic
and are synchronized to the output DATACLK and the digital
pixel data on the output databus. HS
OUT
is used to signal
the start of a new line of digital data. VS
OUT
is not needed in
most applications.
Both HSYNC
OUT
and VSYNC
OUT
(including the sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL98001.
HSYNC
OUT
HSYNC
OUT
is an unmodified, buffered version of the incoming
HSYNC
IN
or SOG
IN
signal of the selected channel, with the
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNC
OUT
will be the same format as the incoming
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNC
OUT
will output the entire SOG signal,
including the VSYNC portion, pre-/post-equalization pulses if
present, and Macrovision pulses if present. HSYNC
OUT
remains active when the ISL98001 is in power-down mode.
HSYNC
OUT
is generally used for mode detection.
VSYNC
OUT
VSYNC
OUT
is an unmodified, buffered version of the
incoming VSYNC
IN
signal of the selected channel, with the
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the ISL98001’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the Macrovision section for more
information. VSYNC
OUT
(including the sync separator
function) remains active in power-down mode. VSYNC
OUT
is generally used for mode detection, start of field detection,
and even/odd field detection.
HS
OUT
HS
OUT
is generated by the ISL98001’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
relative to pixel 0. HS
OUT
is used by the scaler to signal the
start of a new line of pixels.
The HS
OUT
Width register (0x19) controls the width of the
HS
OUT
pulse. The pulse width is nominally 1 pixel clock
period times the value in this register. In the 48 bit output
mode (register 0x18[0] = 1), or the YPbPr input mode
(register 0x05[2] = 1), the HS
OUT
width is incremented in 2
pixel clock (1 DATACLK) increments (see Table 8).
VS
OUT
VS
OUT
is generated by the ISL98001’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its leading and trailing edges are
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its
width, in units of lines, is equal to the width of the incoming
VSYNC (See the VSYNC
OUT
description). Its polarity is
determined by register 0x18[6]. Note: This output is not
needed in most applications. Intersil strongly discourages
using this signal - use VSYNC
OUT
instead.
TABLE 8. HS
OUT
WIDTH
HS
OUT
WIDTH (PIXEL CLOCKS)
REGISTER
0x19 VALUE
24-BIT MODE,
RGB
24-BIT MODE,
YPbPr
ALL 48-BIT
MODES
00 10
11 10
22 32
33 32
44 54
55 54
66 76
77 76
ISL98001
26
FN6148.5
September 21, 2010
Crystal Oscillator
An external 22MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
As an alternative to a crystal, the XTAL
IN
pin can be driven
with a 3.3V CMOS-level external clock source at any
frequency between 22MHz and 33.5MHz. The ISL98001’s
jitter specification assumes a low-jitter crystal source. If the
external clock source has increased jitter, the sample clock
generated by the DPLL may exhibit increased jitter as well.
Reset
The ISL98001 has a Power On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET
pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET
pin does not
need to be used in normal operation and can be tied high.
Initialization
The ISL98001 initializes with default register settings for an
AC-coupled, 640x480 RGB input on the VGA1 channel, with
a 24-bit output. An input signal meeting these conditions will
be output on the databus without writing to any of the
configuration registers. The configuration registers will need
to be changed as required to support other resolutions,
different input channels, different sync sources, phase
optimization etc.
The ISL98001-275 requires one additional register write to
operate at their maximum speed. The ISL98001 generates
an internal reference clock equal to the crystal frequency
times the value in register 0x2B (nominally 0x14 or
20 decimal). The typical value of this clock is therefore
500MHz (25MHz*20). The minimum value of this clock is
360MHz.
This internal clock needs to be greater than 2 times the PLL
pixel rate. The nominal value of 500MHz therefore supports
pixel rates up to 250MHz. To achieve pixel rates of 275MHz,
or to work with lower frequency crystals, the multiplier in
register 0x2B must be programmed using Equation 2:
For example, if the maximum pixel clock is 263MHz (QXGA),
and the crystal frequency is 24MHz, then register 0x2B
should be set to 1 + INT(2*263/24) = 1 + INT(21.917) =
1 + 21 = 22 = 0x16. Table 9 illustrates the compensation
values required to operate the ISL98001-275 at its maximum
speed of 275MHz. If lower maximum Pixel Clock frequencies
are needed, using the formula above to reduce the value of
register 0x2B will reduce power consumption.
Reducing Power Dissipation
It is possible to reduce the total power consumption of the
ISL98001 in applications where power is a concern. There are
several techniques that can be used to reduce power
consumption:
• Internal Digital Voltage Regulator. The ISL98001 features
a 3.3V to 1.9V voltage regulator (pins VREG
IN
and
VREG
OUT
) for the low voltage digital supply. This regulator
typically sources 100mA at 1.9V, dissipating up to 140mW in
heat. Providing an external, clean 1.8V supply to the V
CORE
,
V
PLL
, and V
COREADC
will substantially reduce power
dissipation. The external 1.8V supply should ramp up after
(or at the same time as) the digital 3.3V (V
D
) supply.
• Internal Analog Voltage Regulator. The ISL98001 also
features a 3.3V to 1.9V voltage regulator for the low voltage
analog supply. This voltage appears on the V
BYPASS
pins.
Unlike the digital low voltage supply, there are no “in” and
“out” connections for this regulator. However, this internal
regulator can only source voltage, and can be effectively
bypassed by driving the V
BYPASS
pins with an external,
clean 2.0V supply. The external 2.0V supply should ramp up
after (or at the same time as) the analog 3.3V (V
A
) supply.
• Buffering Digital Outputs. Switching 24 or 48 data output
pins into a capacitive bus can consume significant current.
The higher the capacitance on the external databus, the
higher the switching current. To minimize current
consumption inside the ISL98001, minimize bus capacitance
and/or insert data buffers such as the SN64AVC16827
between the ISL98001’s data outputs and the external
databus.
• Internal Reference Frequency. The crystal frequency is
multiplied by the value in register 0x2B to generate an
internal high frequency reference clock. For pixel rates up to
160MHz, this internal frequency should be set to 400MHz
±10% for minimum power consumption. For example, for a
33MHz frequency at XTAL
IN
, register 0x2B should be set to
a value of 0x0C to minimize power. For pixel rates greater
than 160MHz, the register 0x2B value should be set using
Equation 2 in the “Initialization” section on page 26.
Standby Mode
The ISL98001 can be placed into a low power standby mode
by writing a 0x0F to register 0x1B, powering down the triple
ADCs, the DPLL, and most of the internal clocks.
0x2B value INT 2
f
MAX_PIXELCLK
f
CRYSTAL
-----------------------------------------
⎝⎠
⎜⎟
⎛⎞
1+=
(EQ. 2)
TABLE 9. CRYSTAL MULTIPLIER FOR 275MHz PIXEL RATE
CRYSTAL FREQUENCY RANGE
(MHz)
REGISTER 0x2B
VALUE
DECIMAL HEX
23 to 23.9 24 0x18
23.9 to 25 23 0x17
25.0 to 26.2 22 0x16
26.2 to 27 21 0x15
ISL98001
27
FN6148.5
September 21, 2010
To allow input monitoring and mode detection during
power-down, the following blocks remain active:
• Serial interface (including the crystal oscillator) to enable
register read/write activity
• Activity and polarity detect functions (registers 0x01 and
0x02)
• The HSYNC
OUT
and VSYNC
OUT
pins (for mode
detection)
EMI Considerations
There are two possible sources of EMI on the ISL98001:
Crystal oscillator. The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low voltage
sine wave oscillator circuit, instead of the typical high-gain
square wave inverter-type oscillator, so there are no harmonics.
Note: The crystal oscillator is not a significant source of EMI.
Digital output switching. This is the largest potential source of
EMI. However, the EMI is determined by the PCB layout and
the loading on the databus. The way to control this is to put
series resistors on the output of all the digital pins (as our demo
board and reference circuits show). These resistors should be
as large as possible, while still meeting the setup and hold
timing requirements of the scaler. We recommend starting with
22Ω. If the databus is heavily loaded (long traces, many other
part on the same bus), this value may need to be reduced. If
the databus is lightly loaded, it may be increased.
Intersil’s recommendations to minimize EMI are:
• Minimize the databus trace length
• Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of the
digital output series resistors to reduce slew rates on the bus.
This can only be done as long as the scaler’s setup and hold
timing requirements continue to be met.
ISL98001 Serial Communication
Overview
The ISL98001 uses a 2-wire serial bus for communication
with its host. SCL is the Serial Clock line, driven by the host,
and SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1) The Host selects the ISL98001 it wishes to communicate
with.
2) The Host writes the initial ISL98001 Configuration
Register address it wishes to write to or read from.
3) The Host writes to or reads from the ISL98001’s
Configuration Register. The ISL98001’s internal address
pointer auto increments, so to read registers 0x00 through
0x1B, for example, one would write 0x00 in step 2, then
repeat step three 28 times, with each read returning the
next register value.
The ISL98001 has a 7-bit address on the serial bus. The
upper 6-bits are permanently set to 100110, with the lower
bit determined by the state of pin 48 (SADDR). This allows
two ISL98001s to be independently controlled while sharing
the same bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 9).
The ISL98001 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W
bit, indicating if the next
transaction will be a Read (R/W
= 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 10).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 9), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 11). To achieve this, data being written to the
ISL98001 is latched on a delayed version of the rising edge
of SCL. SCL is delayed and deglitched inside the ISL98001
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL98001 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 12 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 13 shows two views of the steps necessary to read
one or more words from the Configuration Register.
ISL98001
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ISL98001CQZ-210

Mfr. #:
Buy ISL98001CQZ-210
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98001CQZ TRPL VID DIGIZER W/DIGTL PLL
Lifecycle:
New from this manufacturer.
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