ISL98001CQZ-210 Datasheet ISL98001CQZ-170, ISL98001IQZ-140, ISL98001CQZ-275 | P22-P24

FN6148.5

September 21, 2010

PGA

The ISL98001’s Programmable Gain Amplifier (PGA) has a

nominal gain range from 0.5V/V (-6dB) to 2.0V/V (+6dB).

The transfer function is in Equation 1:

where GainCode is the value in the Gain register for that

particular color. Note that for a gain of 1V/V, the GainCode

should be 85 (0x55). This is a different center value than the

128 (0x80) value used by some other AFEs, so the firmware

should take this into account when adjusting gains.

The PGAs are updated by the internal clamp signal once per

line. In normal operation this means that there is a maximum

delay of one HSYNC period between a write to a Gain

in that channel’s actual PGA gain. If there is no regular

HSYNC/SOG source, or if the external clamp option is

enabled (register 0x13[5:4]) but there is no external clamp

signal being generated, it may take up to 100ms for a write

to the Gain register to update the PGA. This is not an issue

in normal operation with RGB and YPbPr signals.

Bandwidth and Peaking Control

input bandwidth to be adjusted with three bit resolution

between its default value (0x0E = 780MHz) and its minimum

bandwidth (0x00, for 100MHz). Typically the higher the

resolution, the higher the desired input bandwidth. To

minimize noise, video signals should be digitized with the

minimum bandwidth setting that passes sharp edges.

Table 4 shows the corner frequencies for different register

settings.

high frequencies to be boosted, restoring some of the

harmonics lost due to excessive EMI filtering, cable losses, etc.

This control has a very large range, and can introduce high

frequency noise into the image, so it should be used judiciously,

or as an advanced user adjustment.

Table 5 shows the corner frequency of the zero for different

peaking register settings. Values above 0x2 may cause

excessive noise, depending on the quality of the input signal

and the PCB environment.

Offset DAC

The ISL98001 features a 10-bit Digital-to-Analog Converter

(DAC) to provide extremely fine control over the full channel

offset. The DAC is placed after the PGA to eliminate

interaction between the PGA (controlling “contrast”) and the

Offset DAC (controlling “brightness”).

In normal operation, the Offset DAC is controlled by the

ABLC circuit, ensuring that the offset is always reduced to

sub-LSB levels (See“Automatic Black Level Compensation

(ABLC™)” on page 23). When ABLC is enabled, the Offset

registers (0x09, 0x0A, 0x0B) control a digital offset added

to or subtracted from the output of the ADC. This mode

provides the best image quality and eliminates the need for

any offset calibration.

If desired, ABLC can be disabled (0x17[0] = 1) and the

Offset DAC programmed manually, with the 8 most

TABLE 4. BANDWIDTH CONTROL

0x0D[3:0] VALUE

(LSB = “x” = “don’t care”) AFE BANDWIDTH

000x 100MHz

001x 130MHz

010x 150MHz

011x 180MHz

100x 230MHz

101x 320MHz

110x 480MHz

111x 780MHz

Gain

----

⎝⎠

⎛⎞

0.5

GainCode

170

-----------------------------+=

(EQ. 1)

TABLE 5. PEAKING CORNER FREQUENCIES

0X0D[7:4] VALUE ZERO CORNER FREQUENCY

0x0 Peaking disabled

0x1 800MHz

0x2 400MHz

0x3 265MHz

0x4 200MHz

0x5 160MHz

0x6 135MHz

0x7 115MHz

0x8 100MHz

0x9 90MHz

0xA 80MHz

0xB 70MHz

0xC 65MHz

0xD 60MHz

0xE 55MHz

0xF 50MHz

ISL98001

FN6148.5

September 21, 2010

significant bits in registers 0x09, 0x0A, 0x0B, and the 2 least

significant bits in register 0x0C[7:2].

The default Offset DAC range is ±127 ADC LSBs. Setting

0x0C[0] = 1 reduces the swing of the Offset DAC by 50%,

making 1 Offset DAC LSB the weight of 1/8th of an ADC

LSB. This provides the finest offset control and applies to

both ABLC and manual modes.

Automatic Black Level Compensation (ABLC™)

ABLC is a function that continuously removes all offset

errors from the incoming video signal by monitoring the

offset at the output of the ADC and servoing the 10-bit

analog DAC to force those errors to zero. When ABLC is

enabled, the user offset control is a digital adder, with 8-bit

resolution (refer to Table 6).

When the ABLC function is enabled (0x17[0] = 0), the ABLC

function is executed every line after the trailing edge of

HSYNC. If register 0x05[5] = 0 (the default), the ABLC

function will be not be triggered while the DPLL is coasting,

preventing any composite sync edges, equalization pulses,

or Macrovision signals from corrupting the black data and

potentially adding a small error in the ABLC accumulator.

After the trailing edge of HSYNC, the start of ABLC is

delayed by the number of pixels specified in registers 0x14

and 0x15. After that delay, the number of pixels specified

by register 0x17[3:2] are averaged together and added to

the ABLC’s accumulator. The accumulator stores the

average black levels for the number of lines specified by

DAC value.

The default values provide excellent results with offset

stability and absolute accuracy better than 1 ADC LSB for

most input signals.

ADC

The ISL98001 features 3 fully differential, high-speed 8-bit

ADCs.

Clock Generation

A Digital Phase Lock Loop (DPLL) is employed to generate

the pixel clock frequency. The HSYNC input and the external

XTAL provide a reference frequency to the PLL. The PLL

then generates the pixel clock frequency that equal to the

incoming HSYNC frequency times the HTOTAL value

programmed into registers 0x0E and 0x0F.

The stability of the clock is very important and correlates

directly with the quality of the image. During each pixel time

transition, there is a small window where the signal is

slewing from the old pixel amplitude and settling to the new

pixel value. At higher frequencies, the pixel time transitions

at a faster rate, which makes the stable pixel time even

smaller. Any jitter in the pixel clock reduces the effective

stable pixel time and thus the sample window in which pixel

sampling can be made accurately.

Sampling Phase

The ISL98001 provides 64 low-jitter phase choices per pixel

period, allowing the firmware to precisely select the optimum

sampling point. The sampling phase register is 0x10.

External Pixel Clock

The ISL98001 can bypass the PLL and use an external clock

signal to drive the ADCs but when this is done the

programmable sample phase is not available. When bits

[5:4] of register 0x13 are set to 11 a clock signal on the

CLOCKINV

pin is used.

HSYNC Slicer

To further minimize jitter, the HSYNC inputs are treated as

analog signals, and brought into a precision slicer block with

thresholds programmable in 400mV steps with 240mV of

hysteresis, and a subsequent digital glitch filter that ignores

any HSYNC transitions within 100ns of the initial transition.

This processing greatly increases the AFE’s rejection of

ringing and reflections on the HSYNC line and allows the

AFE to perform well even with pathological HSYNC signals.

Voltages given above and in the HSYNC Slicer register

description are with respect to a 3.3V sync signal at the

HSYNC

input pin. To achieve 5V compatibility, a 680Ω

series resistor should be placed between the HSYNC source

and the HSYNC

input pin. Relative to a 5V input, the

hysteresis will be 240mV*5V/3.3V = 360mV, and the slicer

step size will be 400mV*5V/3.3V = 600mV per step.

TABLE 6. OFFSET DAC RANGE AND OFFSET DAC ADJUSTMENT

OFFSET

DAC RANGE

0X0C[0]

10-BIT

OFFSET DAC

RESOLUTION

ABLC

0x17[0]

USER OFFSET CONTROL RESOLUTION

USING REGISTERS 0x09 - 0X0B ONLY

(8-BIT OFFSET CONTROL)

USER OFFSET CONTROL RESOLUTION

USING REGISTERS 0X09 - 0x0B AND

0X0C[7:2](10-BIT OFFSET CONTROL)

0 0.25 ADC LSBs

(0.68mV)

(ABLC on)

1 ADC LSB

(digital offset control)

N/A

1 0.125 ADC LSBs

(0.34mV)

(ABLC on)

1 ADC LSB

(digital offset control)

N/A

0 0.25 ADC LSBs

(0.68mV)

(ABLC off)

1.0 ADC LSB

(analog offset control)

0.25 ADC LSB

(analog offset control)

1 0.125 ADC LSBs

(0.34mV)

(ABLC off)

0.5 ADC LSB

(analog offset control)

0.125 ADC LSB

(analog offset control)

ISL98001

FN6148.5

September 21, 2010

SOG Slicer

The SOG input has programmable threshold, 40mV of

hysteresis, and an optional low pass filter that can be used to

remove high frequency video spikes (generated by overzealous

video peaking in a DVD player, for example) that can cause

false SOG triggers. The SOG threshold sets the comparator

threshold relative to the sync tip (the bottom of the SOG pulse).

SYNC Status and Polarity Detection

The SYNC Status register (0x01) and the SYNC Polarity

(VSYNC

, HSYNC

, and SOG

for each of 2 channels)

and report their status. However, accurate sync activity

detection is always a challenge. Noise and repetitive video

patterns on the Green channel may look like SOG activity

when there actually is no SOG signal, while non-standard

SOG signals and trilevel sync signals may have amplitudes

below the default SOG slicer levels and not be easily

detected. As a consequence, not all of the activity detect bits

in the ISL98001 are correct under all conditions.

Table 7 shows how to use the SYNC Status register (0x01)

to identify the presence of and type of a sync source. The

firmware should go through the table in the order shown,

stopping at the first entry that matches the activity indicators

in the SYNC Status register.

Final validation of composite sync sources (SOG or

Composite sync on HSYNC) should be done by setting the

Input Configuration register (0x05) to the composite sync

source determined by this table, and confirming that the

CSYNC detect bit is set.

The accuracy of the Trilevel Sync detect bit can be increased

by multiple reads of the Trilevel Sync detect bit. See the

Trilevel Sync Detect section for more details.

For best SOG operation, the SOG low pass filter (register

0x04[4] should always be enabled to reject the high

frequency peaking often seen on video signals.

HSYNC and VSYNC Activity Detect

Activity on these bits always indicates valid sync pulses, so

they should have the highest priority and be used even if the

SOG activity bit is also set.

SOG Activity Detect

The SOG activity detect bit monitors the output of the SOG

slicer, looking for 64 consecutive pulses with the same period

and duty cycle. If there is no signal on the Green (or Y)

channel, the SOG slicer will clamp the video to a DC level and

will reject any sporadic noise. There should be no false

positive SOG detects if there is no video on Green (or Y).

If there is video on Green (or Y) with no valid SOG signal,

the SOG activity detect bit may sometimes report false

positives (it will detect SOG when no SOG is actually

present). This is due to the presence of video with a

repetitive pattern that creates a waveform similar to SOG.

For example, the desktop of a PC operating system is black

during the front porch, horizontal sync, and back porch, then

increases to a larger value for the video portion of the

screen. This creates a repetitive video waveform very similar

to SOG that may falsely trigger the SOG Activity detect bit.

However, in these cases where there is active video without

SOG, the SYNC information will be provided either as

separate H and V sync on HSYNC

and VSYNC

, or

composite sync on HSYNC

. HSYNC

and VSYNC

should therefore be used to qualify SOG. The SOG Active bit

should only be considered valid if HSYNC Activity

Detect = 0. Note: Some pattern generators can output

HSYNC and SOG simultaneously, in which case both the

HSYNC and the SOG activity bits will be set, and valid. Even

in this case, however, the monitor should still choose

HSYNC over SOG.

TriLevel Sync Detect

Unlike SOG detect, the TriLevel Sync detect function does

not check for 64 consecutive trilevel pulses in a row, and is

therefore less robust than the SOG detect function. It will

report false positives for SOG-less video for the same

reasons the SOG activity detect does, and should therefore

be qualified with both HSYNC and SOG. TriLevel Sync

Detect should only be considered valid if HSYNC Activity

Detect = 0 and SOG Activity Detect = 1.

If there is a SOG signal, the TriLevel Detect bit will operate

correctly for standard trilevel sync levels (600mV

P-P

). In

some real-world situations, the peak-to-peak sync amplitude

TABLE 7. SYNC SOURCE DETECTION TABLE

HSYNC

DETECT

VSYNC

DETECT

SOG

DETECT

TRILEVEL

DETECT RESULT

1 1 X X Sync is on HSYNC and VSYNC

1 0 X X Sync is composite sync on HSYNC. Set Input configuration register to CSYNC on

HSYNC and confirm that CSYNC detect bit is set.

0 0 1 0 Sync is composite sync on SOG. It is possible that trilevel sync is present but amplitude

is too low to set trilevel detect bit. Use video mode table to determine if this video mode

is likely to have trilevel sync, and set clamp start, width values appropriately if it is.

0 0 1 1 Sync is composite sync on SOG. Sync is likely to be trilevel.

0 0 0 X No valid sync sources on any input.

ISL98001

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

ISL98001CQZ-210

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

Analog Front End - AFE ISL98001CQZ TRPL VID DIGIZER W/DIGTL PLL

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ISL98001CQZ-210

ISL98001CQZ-210

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