19
FN6148.5
September 21, 2010
Automatic Black Level Compensation (ABLC™)
and Gain Control
Traditional video AFEs have an offset DAC prior to the ADC,
to both correct for offsets on the incoming video signals and
add/subtract an offset for user “brightness control” without
sacrificing the 8-bit dynamic range of the ADC. This solution
is adequate, but it places significant requirements on the
system's firmware, which must execute a loop that detects
the black portion of the signal and then servos the offset
DACs until that offset is nulled (or produces the desired ADC
output code). Once this has been accomplished, the offset
(both the offset in the AFE and the offset of the video card
generating the signal) is subject to drift - the temperature
inside a monitor or projector can easily change +50°C
between power-on/offset calibration on a cold morning and
the temperature reached once the monitor and the monitor's
environment have reached steady state. Offset can drift
significantly over +50°C, reducing image quality and
requiring that the user do a manual calibration once the
monitor has warmed up.
In addition to drift, many AFEs exhibit interaction between
the offset and gain controls. When the gain is changed, the
magnitude of the offset is changed as well. This again
increases the complexity of the firmware as it tries to
optimize gain and offset settings for a given video input
signal. Instead of adjusting just the offset, then the gain, both
have to be adjusted interactively until the desired ADC
output is reached.
The ISL98001 simplifies offset and gain adjustment and
completely eliminates offset drift using its Automatic Black
Level Compensation (ABLC™) function. ABLC monitors the
black level and continuously adjusts the ISL98001's 10-bit
offset DACs to null out the offset. Any offset, whether due to
the video source or the ISL98001's analog amplifiers, is
eliminated with 10-bit (1/4 of an ADC LSB) accuracy. Any drift
is compensated for well before it can have a visible effect.
Manual offset adjustment control is still available - an 8-bit
register allows the firmware to adjust the offset ±64 codes in
exactly 1 ADC LSB increments. And gain is now completely
independent of offset - adjusting the gain no longer affects the
offset, so there is no longer a need to program the firmware to
cope with interactive offset and gain controls.
Finally, there should be no concerns over ABLC itself
introducing visible artifacts; it doesn't. ABLC functions at a
very low frequency, changing the offset in 1/4 LSB
increments, so it can't cause visible brightness fluctuations.
And once ABLC is locked, if the offset doesn't drift, the DACs
won't change. If desired, ABLC can be disabled, allowing the
firmware to work in the traditional way, with 10-bit offset
DACs under the firmware's control.
Gain and Offset Control
To simplify image optimization algorithms, the ISL98001
features fully-independent gain and offset adjustment.
Changing the gain does not affect the DC offset, and the
weight of an Offset DAC LSB does not vary depending on
the gain setting.
The full-scale gain is set in the three 8-bit registers
(0x06-0x08). The ISL98001 can accept input signals with
amplitudes ranging from 0.35V
P-P
to 1.4V
P-P
.
The offset controls shift the entire RGB input range, changing
the input image brightness. Three separate registers provide
independent control of the R, G, and B channels. Their
nominal setting is 0x80, which forces the ADC to output code
0x00 (or 0x80 for the R (Pr) and B (Pb) channels in YPbPr
mode) during the back porch period when ABLC is enabled.
Functional Description
Inputs
The ISL98001 digitizes analog video inputs in both RGB
and Component (YPbPr) formats, with or without
embedded sync (SOG).
RGB Inputs
For RGB inputs, the black/blank levels are identical and equal
to 0V. The range for each color is typically 0V to 0.7V from
black to white. HSYNC and VSYNC are separate signals.
Component YPbPr Inputs
In addition to RGB and RGB with SOG, the ISL98001 has an
option that is compatible with the component YPbPr video
inputs typically generated by DVD players. While the
ISL98001 digitizes signals in these color spaces, it does not
perform color space conversion; if it digitizes an RGB signal,
it outputs digital RGB, while if it digitizes a YPbPr signal, it
outputs digital YCbCr, also called YUV.
The Luminance (Y) signal is applied to the Green channel
and is processed in a manner identical to the Green input
with SOG described previously. The color difference signals
Pb and Pr are bipolar and swing both above and below the
black level. When the YPbPr mode is enabled, the black
level output for the color difference channels shifts to a mid
scale value of 0x80. Setting configuration register
0x05[2] = 1 enables the YPbPr signal processing mode of
operation.
TABLE 1. YUV MAPPING (4:4:4)
INPUT
SIGNAL
ISL98001
INPUT
CHANNEL
ISL98001
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y Green Green Y
0
Y
1
Y
2
Y
3
Pb Blue Blue U
0
U
1
U
2
U
3
Pr Red Red V
0
V
1
V
2
V
3
ISL98001
20
FN6148.5
September 21, 2010
The ISL98001 can optionally decimate the incoming data to
provide a 4:2:2 output stream (configuration register
0x18[4] = 1) as shown in Table 2.
There is also a “compatibility mode”, enabled by setting bit 3
of register 0x18 to a 1, that outputs the U and V data with the
format used by the previous generation (“X980xx”) series of
AFEs, shown in Table 3.
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled (See
register 0x05[1]). AC coupling is usually preferred since it
allows video signals with substantial DC offsets to be accurately
digitized. The ISL98001 provides a complete internal
DC-restore function, including the DC restore clamp (See
Figure 7) and programmable clamp timing (registers 0x14,
0x15, 0x16, and 0x23).
When AC-coupled, the DC restore clamp is applied every line,
a programmable number of pixels after the trailing edge of
HSYNC. If register 0x05[5] = 0 (the default), the clamp will not
be applied while the DPLL is coasting, preventing any clamp
voltage errors from composite sync edges, equalization pulses,
or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC Restore
and ABLC Starting Pixel registers (0x14 and 0x15) has been
reached. The clamp is applied for the number of pixels
specified by the DC Restore Clamp Width Register (0x16). The
clamp can be applied to the back porch of the video, or to the
front porch (by increasing the DC Restore and ABLC Starting
Pixel registers so all the active video pixels are skipped).
If DC-coupled operation is desired, the input to the ADC will be
the difference between the input signal (R
IN
1, for example) and
that channel’s ground reference (RGB
GND
1 in that example).
SOG
For component YPbPr signals, the sync signal is embedded
on the Y channel’s video, which is connected to the green
input, hence the name SOG (Sync on Green). The horizontal
sync information is encoded onto the video input by adding
the sync tip during the blanking interval. The sync tip level is
typically 0.3V below the video black level.
To minimize the loading on the Green channel, the SOG input
for each of the green channels should be AC-coupled to the
ISL98001 through a series combination of a 10nF capacitor
and a 500Ω resistor. Inside the ISL98001, a window
comparator compares the SOG signal with an internal 4-bit
programmable threshold level reference ranging from 0mV to
300mV below the minimum sync level. The SOG threshold
level, hysteresis, and low-pass filter is programmed via
register 0x04. If the Sync-On-Green function is not needed,
the SOG
IN
pin(s) may be left unconnected.
SYNC Processing
The ISL98001 can process sync signals from 3 different
sources: discrete HSYNC and VSYNC, composite sync on
TABLE 2. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL98001
INPUT
CHANNEL
ISL98001
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y Green Green Y
0
Y
1
Y
2
Y
3
Pb Blue Blue driven low
Pr Red Red U
0
V
0
U
2
V
2
TABLE 3. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL98001
INPUT
CHANNEL
ISL98001
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y Green Green Y
0
Y
1
Y
2
Y
3
Pb Blue Blue driven low
Pr Red Red U
0
V
1
U
2
V
3
R(GB)
IN
1
CLAMP
GENERATION
R(GB)
GND
1
R(GB)
IN
2
R(GB)
GND
2
VGA1
VGA2
V
IN
+
V
IN
-
DC Restore
Clamp DAC
V
CLAMP
8 bit ADC
Offset
DAC
Fixed
Offset
ABLC™
ABLC™
Offset
Control
Registers
ABLC™
Fixed
Offset
0x00
To
ABLC
Block
To Output
Formatter
10
10
10
8 8
8
8
Automatic Black Level
Compensation (ABLC™) Loop
DC Restoration
Input
Bandwidth
PGA
Bandwidth
Control
8
FIGURE 7. VIDEO FLOW (INCLUDING ABLC)
ISL98001
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FN6148.5
September 21, 2010
the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
ISL98001 has SYNC activity detect functions to help the
firmware determine which sync source is available.
Macrovision
The ISL98001 automatically detects the presence of
Macrovision-encoded video. When Macrovision is detected,
it generates a mask signal that is ANDed with the incoming
SOG CSYNC signal to remove the Macrovision before the
HSYNC goes to the PLL. No additional programming is
required to support Macrovision.
If desired (it is never necessary in normal operation), this
function can be disabled by setting the Sync Mask Disable
(register 0x05 bit 6) to a 1.
The mask signal is also applied to the HSYNC
OUT
signal.
When Sync Mask Disable = 0, any Macrovision present on
the incoming sync will not be visible on HSYNC
OUT
. If the
application requires the Macrovision pulses to be visible on
HSYNC
OUT
, set the HSYNC
OUT
Mask Disable bit (register
0x05 bit 7).
Headswitching from Analog Videotape Signals
Occasionally this AFE may be used to digitize signals
coming from analog videotape sources. The most common
example of this is a Digital VCR (which for best signal quality
would be connected to this AFE with a component YPbPr
connection). If the digital VCR is playing an older analog
VHS tape, the sync signals from the VCR may contain the
worst of the traditional analog tape artifacts: headswitching.
Headswitching is traditionally the enemy of PLLs with large
capture ranges, because a headswitch can cause the
HSYNC period to change by as much as ±90%. To the PLL,
this can look like a frequency change of -50% to greater than
+900%, causing errors in the output frequency (and
obviously the phase) to change. Subsequent HSYNCs have
the correct, original period, but most analog PLLs will take
dozens of lines to settle back to the correct frequency and
phase after a headswitch disturbance. This causes the top of
the image to “tear” during normal playback. In “trick modes”
(fast forward and rewind), the HSYNC signal has multiple
headswitch-like discontinuities, and many PLLs never settle
to the correct value before the next headswitch, rendering
the image completely unintelligible.
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x1C to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting this high will slightly increase jitter, the default setting
(0x49) for register 0x1C is recommended for all other sync
sources.
0:
VGA1
0x05[0]
1:
VGA2
HSYNC
IN
1
HSYNC1
SLICER
0x03[2:0]
VSYNC
IN
1
SOG
IN
1
HSYNC2
SLICER
0x03[6:4]
HSYNC
IN
VSYNC
IN
ACTIVITY 0x01[6:0]
&
POLARITY 0x02[5:0]
DETECT
HSYNC
IN
2
VSYNC
IN
2
SOG
IN
2
SYNC
SPLITTER
PLL
0x0E through 0x13
HSYNC
OUT
VSYNC
OUT
COAST
GENERATION
0x11, 0x12
XTAL
IN
XTAL
OUT
0: ÷1
0x13
[6]
1: ÷2
÷2
XTALCLOCK
OUT
Output
Formatter
0x18,
0x19,
0x1A
Pixel Data
from AFE
24
R
P
[7:0]
R
S
[7:0]
G
P
[7:0]
G
S
[7:0]
B
P
[7:0]
B
S
[7:0]
DATACLK
HS
OUT
VS
OUT
SOG
IN
SOG
SLICER
0x04[3:0]
SOG
SLICER
0x04[3:0]
00, 10,
11:
HSYNC
IN
0x05[4:3]
01:
SOG
IN
1:
SYNC
SPLTR
0x05[3]
0:
VSYNC
IN
CLOCKINV
IN
HS
PIXCLK
CSYNC
SOURCE
SYNC
TYPE
VSYNC
DATACLK
FIGURE 8. SYNC FLOW
ISL98001

ISL98001CQZ-210

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98001CQZ TRPL VID DIGIZER W/DIGTL PLL
Lifecycle:
New from this manufacturer.
Delivery:
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