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ISL98001CQZ-210

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
7
FN6148.5
September 21, 2010
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
8.5 DATACLK Pipeline Latency
P
10
P
11
P
12
HSYNC
IN
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
G
0
(Y
o
) G
1
(Y
1
)G
2
(Y
2
)
B
0
(U
o
)R
1
(V
1
)B
2
(U
2
)
G
P
[7:0]
R
P
[7:0]
B
P
[7:0]
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 4. 24-BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +10.5)*t
PIXEL
D
1
D
3
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
D
0
R
P
/G
P
/B
P
[7:0]
HS
OUT
P
10
P
11
P
12
D
2
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
R
S
/G
S
/B
S
[7:0]
HSYNC
IN
FIGURE 5. 48-BIT OUTPUT MODE
ISL98001
8
FN6148.5
September 21, 2010
Programmable
Width and Polarity
Analog
Video In
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
8
P
0
P
9
HS
OUT
P
10
P
11
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
DATACLK
HSYNC
IN
D
0
R
P
/G
P
/B
P
[7:0] D
2
D
1
R
S
/G
S
/B
S
[7:0]
t
HSYNCin-to-HSout
= 7.5ns + (PHASE/64 +8.5)*t
PIXEL
FIGURE 6. 48-BIT OUTPUT MODE, INTERLEAVED TIMING
ISL98001
9
FN6148.5
September 21, 2010
Pin Configuration (MQFP, ISL98001)
B
S
7
B
S
6
B
S
5
B
S
4
B
S
3
B
S
2
B
S
1
B
S
0
GND
D
V
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
37
34
35
36
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
GND
A
V
BYPASS
GND
A
NC
V
A
R
IN
1
GND
A
V
BYPASS
NC
GND
A
V
A
G
IN
1
RGB
GND
1
SOG
IN
1
GND
A
V
BYPASS
GND
A
V
A
B
IN
1
V
A
GND
A
R
IN
2
GND
A
G
IN
2
RGB
GND
2
SOG
IN
2
B
IN
2
GND
D
V
COREADC
V
A
GND
A
XTAL
IN
XTAL
OUT
GND
X
V
X
CLOCKINV
IN
HSYNC
IN
1
HSYNC
IN
2
V
PLL
GND
D
VSYNC
IN
1
VSYNC
IN
2
RESET
XCLK
OUT
SADDR
SDA
SCL
GND
D
V
CORE
NC
VREG
IN
GND
D
B
P
7
B
P
6
B
P
5
B
P
4
B
P
3
B
P
2
B
P
1
B
P
0
GND
D
V
D
GND
D
V
CORE
G
S
7
G
S
6
G
S
5
G
S
4
G
S
3
G
S
2
G
S
1
G
S
0
G
P
7
G
P
6
G
P
5
G
P
4
G
P
3
G
P
2
G
P
1
G
P
0
GND
D
V
D
R
S
7
R
S
6
R
S
5
R
S
3
R
S
2
R
S
1
R
S
0
GND
D
V
CORE
GND
D
V
D
R
P
7
R
P
6
R
P
5
R
P
4
R
P
3
R
P
2
R
P
1
R
P
0
DATACLK
DATACLK
GND
D
V
D
HS
OUT
HSYNC
OUT
VSYNC
OUT
VS
OUT
GND
A
GND
D
R
S
4
V
D
GND
D
V
D
V
A
GND
A
VREG
OUT
ISL98001
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

ISL98001CQZ-210

Mfr. #:
Buy ISL98001CQZ-210
Manufacturer:
Renesas / Intersil
Description:
Analog Front End - AFE ISL98001CQZ TRPL VID DIGIZER W/DIGTL PLL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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