5
FN6148.5
September 21, 2010
I
D
Digital Supply Current With grayscale ramp input 200 mA
I
X
Crystal Oscillator Supply Current 1.4 2 mA
P
D
Total Power Dissipation
ISL98001-140 With grayscale ramp input 0.95 1.10 W
ISL98001-170 With grayscale ramp input 1.05 1.15 W
ISL98001-210 With grayscale ramp input 1.10 1.20 W
ISL98001-275 With grayscale ramp input 1.20 1.30 W
Standby Mode ADCs, PLL powered down 50 80 mW
AC TIMING CHARACTERISTICS
PLL Jitter 250 450 ps p-p
Sampling Phase Steps 5.6° per step 64
Sampling Phase Tempco ±1 ps/°C
Sampling Phase
Differential Nonlinearity
Degrees out of 360° ±3 °
HSYNC Frequency Range 10 150 kHz
f
XTAL
Crystal Frequency Range 23 25 27 MHz
f
XTALIN
Frequency Range with External 3.3V Clock
Signal Driving XTAL
IN
23 25 33.5 MHz
t
SETUP
DATA Valid Before Rising Edge of
DATACLK
15pF DATACLK load, 15pF DATA
load (Note 2)
1.3 ns
t
HOLD
DATA Valid After Rising Edge of DATACLK 15pF DATACLK load, 15pF DATA
load (Note 2)
2.0 ns
AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)
f
SCL
SCL Clock Frequency 0 400 kHz
Maximum Width of a Glitch on SCL that Will
be Suppressed
2 XTAL periods min 80 ns
t
AA
SCL LOW to SDA Data Out Valid 5 XTAL periods plus SDA’s RC
time constant
Refer to
comment
µs
t
BUF
Time the Bus Must be Free Before a New
Transmission Can Start
1.3 µs
t
LOW
Clock LOW Time 1.3 µs
t
HIGH
Clock HIGH Time 0.6 µs
t
SU:STA
Start Condition Setup Time 0.6 µs
t
HD:STA
Start Condition Hold Time 0.6 µs
t
SU:DAT
Data In Setup Time 100 ns
t
HD:DAT
Data In Hold Time 0 ns
t
SU:STO
Stop Condition Setup Time 0.6 µs
t
DH
Data Output Hold Time 4 XTAL periods min 160 ns
NOTE:
2. Setup and hold times are specified for a 170MHz DATACLK rate.
Electrical Specifications Specifications apply for V
A
= V
D
= V
X
= 3.3V, pixel rate = 140MHz for ISL98001-140, 170MHz for
ISL98001-170, 210MHz for ISL98001-210, or 275MHz for ISL98001-275, f
XTAL
= 25MHz, T
A
= +25°C, unless
otherwise noted. (Continued)
SYMBOL PARAMETER COMMENT MIN TYP MAX UNIT
ISL98001
