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PTN3460BS/F4Y

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 10 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
8.2 LVDS transmitter
The LVDS interface can operate either in Single or Dual LVDS Bus mode at pixel clock
frequencies over the range of 25 MHz to 112 MHz and color depths of 18 bpp or 24 bpp.
Each LVDS bus consists of 3/4 differential data pairs and one clock pair. PTN3460 can
packetize RGB video data, HSYNC, VSYNC, DE either in VESA or JEIDA format. To
enable system EMI reduction, the device can be programmed for center spreading of
LVDS channel clock outputs.
The LVDS interface can be flexibly configured using multi-level configuration pins (CFG1,
CFG2, CFG3, CFG4) or via register interface. The configuration pins and the
corresponding definitions are described in Table 3
through Table 6. Nevertheless, as the
configuration pins are designed for general purpose, their definitions can be modified and
they can be used for any other purposes. However, this can be achieved through firmware
upgrade only.
[1] LVDS center spreading modulation frequency is kept at 32.9 kHz.
[1] Pull-up/down resistor value in the range of 1 k to 10 k.
Table 3. CFG1 configuration options
Configuration input setting Number of LVDS links
LOW single LVDS bus
HIGH dual LVDS bus
Table 4. CFG2 configuration options
3-level configuration input setting Data format Number of bits per pixel (bpp)
LOW VESA 24 bpp
open JEIDA 24 bpp
HIGH JEIDA or VESA 18 bpp
Table 5. CFG3 configuration options
[1]
3-level configuration input setting LVDS clock frequency spread depth control
LOW 0 %
open 1 %
HIGH 0.5 %
Table 6. CFG4 configuration options
3-level configuration input setting LVDS output swing (typical value)
pull-down resistor
[1]
to GND 250 mV
open 300 mV
pull-up resistor
[1]
to V
DD(3V3)
400 mV
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 11 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
The VESA and JEIDA data format definitions are described in Table 7 to Table Table 13.
Table 7. LVDS single bus, 18 bpp, VESA or JEIDA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
Table 8. LVDS single bus, 24 bpp, VESA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
LVDS odd differential channel D don’t care
bit 7 bit 6 bit 7 bit 6 bit 7 bit 6
Table 9. LVDS dual bus, 18 bpp, VESA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
LVDS even differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS even differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS even differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
Table 10. LVDS dual bus, 24 bpp, VESA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
LVDS odd differential channel D don’t care
bit 7 bit 6 bit 7 bit 6 bit 7 bit 6
LVDS even differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS even differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS even differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
LVDS even differential channel D don’t care
bit 7 bit 6 bit 7 bit 6 bit 7 bit 6
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 12 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
PTN3460 delivers great flexibility by supporting more programmable options via I
2
C-bus
or AUX interface. Please refer to Section 8.3.8
for more details.
Table 11. LVDS single bus, 24 bpp, JEIDA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
LVDS odd differential channel B
bit 3 bit 2 bit 7 bit 6 bit 5 bit 4 bit 3
LVDS odd differential channel C DE VSYNC HSYNC
bit 7 bit 6 bit 5 bit 4
LVDS odd differential channel D don’t care
bit 1 bit 0 bit 1 bit 0 bit 1 bit 0
Table 12. LVDS dual bus, 18 bpp, JEIDA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS odd differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS odd differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
LVDS even differential channel A
bit 0 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
LVDS even differential channel B
bit 1 bit 0 bit 5 bit 4 bit 3 bit 2 bit 1
LVDS even differential channel C DE VSYNC HSYNC
bit 5 bit 4 bit 3 bit 2
Table 13. LVDS dual bus, 24 bpp, JEIDA data packing
Channel Bit position
6 5 4 3 2 1 0
LVDS odd differential channel A
bit 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
LVDS odd differential channel B
bit 3 bit 2 bit 7 bit 6 bit 5 bit 4 bit 3
LVDS odd differential channel C DE VSYNC HSYNC
bit 7 bit 6 bit 5 bit 4
LVDS odd differential channel D don’t care
bit 1 bit 0 bit 1 bit 0 bit 1 bit 0
LVDS even differential channel A
bit 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2
LVDS even differential channel B
bit 3 bit 2 bit 7 bit 6 bit 5 bit 4 bit 3
LVDS even differential channel C DE VSYNC HSYNC
bit 7 bit 6 bit 5 bit 4
LVDS even differential channel D don’t care
bit 1 bit 0 bit 1 bit 0 bit 1 bit 0
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

PTN3460BS/F4Y

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Manufacturer:
NXP Semiconductors
Description:
Display Interface IC eDP to LVDS bridge IC
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