PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 7 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
LVSCO_P 48 LVDS output Odd bus, Channel C differential signal to LVDS receiver. LVSCO_P makes a
differential pair with LVSCO_N.
LVSCO_N 49 LVDS output Odd bus, Channel C differential signal to LVDS receiver. LVSCO_N makes a
differential pair with LVSCO_P.
LVSCKO_P 46 LVDS clock
output
Odd bus, clock differential signal to LVDS receiver. LVSCKO_P makes a
differential pair with LVSCKO_N.
LVSCKO_N 47 LVDS clock
output
Odd bus, clock differential signal to LVDS receiver. LVSCKO_N makes a
differential pair with LVSCKO_P.
LVSDO_P 43 LVDS output Odd bus, Channel D differential signal to LVDS receiver. LVSDO_P makes a
differential pair with LVSDO_N.
LVSDO_N 44 LVDS output Odd bus, Channel D differential signal to LVDS receiver. LVSDO_N makes a
differential pair with LVSDO_P.
DDC_SDA 30 open-drain
DDC data I/O
DDC data signal connection to display panel. Pulled-up by external termination
resistor (5 V tolerant).
DDC_SCL 29 open-drain
DDC clock I/O
DDC clock signal connection to display panel. Pulled-up by external termination
resistor (5 V tolerant).
Panel and backlight interface signals
PVCCEN 33 CMOS output Panel power (V
CC
) enable output.
PWMO 28 CMOS output PWM output signal to display panel.
BKLTEN 26 CMOS output Backlight enable output.
Control interface signals
PD_N 10 CMOS input Chip power-down input (active LOW). If PD_N is LOW, then the device is in
Deep power-down completely, even if supply rail is ON; for the device to be able
to operate, the PD_N pin must be HIGH.
RST_N 9 CMOS input Chip reset pin (active LOW); internally pulled-up. The pin is meant to reset the
device and all its internal states/logic; all internal registers are taken to default
value after RST_N is applied and made HIGH.
If RST_N is LOW, the device stays in reset condition and for the device to be
able to operate, RST_N must be HIGH.
DEV_CFG 12 CMOS I/O I
2
C-bus address/mode selection pin.
TESTMODE 20 CMOS input If TESTMODE is left open or pulled HIGH, CFG[4:1] operate as JTAG pins. If
TESTMODE is pulled LOW, these pins serve as configuration pins.
CFG1 21 input Behavior defined by TESTMODE pin.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST
CLOCK input. If TESTMODE is pulled LOW, this pin acts as configuration input.
CFG2 22 input Behavior defined by TESTMODE pin.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG MODE
SELECT input. If TESTMODE is pulled LOW, this pin acts as configuration
input.
CFG3 23 input Behavior defined by TESTMODE pin.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST
DATA INPUT. If TESTMODE is pulled LOW, this pin acts as configuration input.
CFG4 27 I/O Behavior defined by TESTMODE pin value.
If TESTMODE is left open or pulled HIGH, this pin functions as JTAG TEST
DATA OUTPUT. If TESTMODE is pulled LOW, this pin acts as configuration
input.
Table 2. Pin description
…continued
Symbol Pin Type Description
