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PTN3460BS/F4Y

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 19 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
10. Limiting values
[1] All voltage values, except differential voltages, are with respect to network ground terminal.
[2] Human Body Model: ANSI/EOS/ESD-S5.1-1994, standard for ESD sensitivity testing, Human Body Model
– Component level; Electrostatic Discharge Association, Rome, NY, USA.
[3] Charged-Device Model: ANSI/EOS/ESD-S5.3-1-1999, standard for ESD sensitivity testing,
Charged-Device Model – Component level; Electrostatic Discharge Association, Rome, NY, USA.
11. Recommended operating conditions
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage
[1]
0.3 +4.6 V
V
I
input voltage 3.3 V CMOS inputs
[1]
0.3 V
DD
+0.5 V
T
stg
storage temperature 65 +150 C
V
ESD
electrostatic discharge
voltage
HBM
[2]
- 8000 V
CDM
[3]
- 1000 V
Table 15. Operating conditions
Over operating free-air temperature range, unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Unit
V
DD(3V3)
supply voltage (3.3 V) 3.0 3.3 3.6 V
V
DD(1V8)
supply voltage (1.8 V) 1.7 1.8 1.9 V
V
I
input voltage 3.3 V CMOS inputs 0 3.3 3.6 V
open-drain I/O with
respect to ground
(e.g., DDC_SCL,
DDC_SDA, MS_SDA,
MS_SCL)
055.5V
T
amb
ambient temperature operating in free air 0 - 70 C
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 20 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
12. Characteristics
12.1 Device characteristics
[1] Time for device to be ready after rising edge of RST_N.
12.2 Power consumption
[1] For Active mode power consumption, LVDS output swing of 300 mV is considered.
Table 16. Device characteristics
Over operating free-air temperature range, unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Unit
t
startup
start-up time device start-up time from power-on and
RST_N = HIGH; supply voltage within
operating range to specified operating
characteristics
--90ms
t
w(rst)
reset pulse width device is supplied with valid supply voltage 10 - - s
t
d(rst)
reset delay time
[1]
device is supplied with valid supply voltage - - 90 ms
t
d(pwrsave-act)
delay time from
power-save to active
time between PD_N going HIGH and HPD
raised HIGH by PTN3460; RST_N is HIGH.
Device is supplied with valid supply voltage.
--90ms
Table 17. Power consumption
At operating free-air temperature of 25
C and under nominal supply value (unless otherwise noted).
Symbol Parameter Conditions Single supply mode
EPS_N = HIGH
or open
Dual supply mode
EPS_N = LOW
Unit
Min Typ Max Min Typ Max
P
cons
power
consumption
Active mode;
1440 900 at 60 Hz;
24 bits per pixel; dual LVDS bus
[1]
- 430 - - 290 - mW
Active mode;
1600 900 at 60 Hz;
24 bits per pixel; dual LVDS bus
[1]
- 448 - - 305 - mW
Active mode;
1920 1200 at 60 Hz;
24-bits per pixel; dual LVDS bus
[1]
- 570 - - 380 - mW
D3 mode/Power-saving mode;
when PTN3460 is set to
Power-saving mode via
‘SET_POWER’ AUX command by
eDP source; AUX and HPDRX
circuitry are only kept active
-27- -15-mW
Deep power-saving/Shutdown mode;
when PD_N is LOW and the device is
supplied with valid supply voltage
-5--2-mW
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 21 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
12.3 DisplayPort receiver characteristics
[1] Range is nominal 350 ppm. DisplayPort channel RX does not require local crystal for channel clock generation.
[2] Up to 0.5 % down spreading is supported. Modulation frequency range of 30 kHz to 33 kHz is supported.
[3] Informative; refer to Figure 6
for definition of differential voltage.
[4] Common-mode voltage is equal to V
bias_RX
voltage.
[5] Total drive current of the input bias circuit when it is shorted to its ground.
[6] Minimum CDR tracking bandwidth at the receiver when the input is repetition of D10.2 symbols without scrambling.
Table 18. DisplayPort receiver main channel characteristics
Over operating free-air temperature range (unless otherwise noted).
Symbol Parameter Conditions Min Typ Max Unit
UI unit interval high bit rate
(2.7 Gbit/s per lane)
[1]
-370-ps
reduced bit rate
(1.62 Gbit/s per lane)
[1]
-617-ps
f
DOWN_SPREAD
link clock down spreading
[2]
0- 0.5%
C
RX
AC coupling capacitor 75 - 200 nF
V
RX_DIFFp-p
differential input peak-to-peak
voltage
at receiver package pins
high bit rate
(2.7 Gbit/s per lane)
[3]
120 - - mV
reduced bit rate
(1.62 Gbit/s per lane)
[3]
40 - - mV
V
RX_DC_CM
RX DC common mode voltage
[4]
0- 2.0V
I
RX_SHORT
RX short-circuit current limit
[5]
--50mA
f
RX_TRACKING_BW
jitter tracking bandwidth
[6]
20 - - MHz
G
eq(max)
maximum equalization gain at 1.35 GHz - 15 - dB
pre-emphasis = 20Log(V
DIFF_PRE
/ V
DIFF
)
Fig 6. Definition of pre-emphasis and differential voltage
002aaf363
V
D+
V
CM
V
D−
V
DIFF_PRE
V
DIFF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

PTN3460BS/F4Y

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Manufacturer:
NXP Semiconductors
Description:
Display Interface IC eDP to LVDS bridge IC
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