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PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 4 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
6. Block diagram
Fig 2. Block diagram of PTN3460
002aaf832
DIFF
RCV
CDR,
S2P
RX PHY
ANALOG
SUBSYSTEM
DIFF
RCV
CDR,
S2P
RCV
PTN3460
DRV
MANCHESTER
CODEC
10b/8b
DE-SCRAM
INTERFACE DE-SKEWING
10b/8b
DE-SCRAM
RX PHY DIGITAL
AUX
CONTROL
DPCD
REGISTERS
DDC
INTERFACE
TIME
CONV.
ISOCHRONOUS LINK
TIMING RECOVERY
MAIN
STREAM
R[7:0]
G[7:0]
B[7:0]
H, V
sync
DDC_SCL
DDC_SDA
V
bias
V
bias
V
bias
DP0_P,
DP0_N
DP1_P,
DP1_N
AUX_P,
AUX_N
HPDRX
supply
SYSTEM
CONTROLLER
LVDS
DIGITAL
SUBSYSTEM
NON-
VOLATILE
MEMORY
I
2
C-BUS
CONTOL
INTERFACE
EDID
EMULATION
LVDS
PHY
SUBSYSTEM
EPS_N PD_N
TESTMODE
CFG1
CFG2
CFG3
CFG4
DEV_CFG
MS_SCL
MS_SDA
LVS[A:D]E_P,
LVS[A:D]E_N
LVSCKE_P,
LVSCKE_N
LVS[A:D]O_P,
LVS[A:D]O_N
LVSCKO_P,
LVSCKO_N
PVCCEN
BKLTEN
PWMO
RST_N
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 5 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
7. Pinning information
7.1 Pinning
Refer to Section 13 “Package outline for package and pin dimensions.
(1) Center pad is connected to PCB ground plane for electrical grounding and thermal relief.
Fig 3. Pin configuration for HVQFN56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AUX_N
AUX_P
GND
DP0_P
DP0_N
V
DD(1V8)
DP1_P
DP1_N
RST_N
PD_N
HPDRX
DEV_CFG
V
DD(3V3)
V
DD(3V3)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
n.c.
n.c.
GNDREG
GNDREG
V
DD(1V8)
TESTMODE
CFG1
CFG2
CFG3
MS_SDA
MS_SCL
BKLTEN
CFG4
PWMO
LVSAE_N
LVSAE_P
LVSBE_N
LVSBE_P
V
DD(3V3)
LVSCE_N
LVSCE_P
LVSCKE_N
LVSCKE_P
PVCCEN
LVSDE_N
LVSDE_P
DDC_SDA
DDC_SCL
42
41
40
39
38
37
36
35
34
33
32
31
30
29
EPS_N
n.c.
LVSAO_N
LVSAO_P
LVSBO_N
LVSBO_P
V
DD(3V3)
LVSCO_N
LVSCO_P
LVSCKO_N
LVSCKO_P
V
DD(1V8)
LVSDO_N
LVSDO_P
56
55
54
53
52
51
50
49
48
47
46
45
44
43
002aaf833
Transparent top view
terminal 1
index area
PTN3460BS
(1)
PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 6 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
7.2 Pin description
Table 2. Pin description
Symbol Pin Type Description
DisplayPort interface signals
DP0_P 4 self-biasing
differential input
Differential signal from DP source. DP0_P makes a differential pair with DP0_N.
The input to this pin must be AC-coupled externally.
DP0_N 5 self-biasing
differential input
Differential signal from DP source. DP0_N makes a differential pair with DP0_P.
The input to this pin must be AC-coupled externally.
DP1_P 7 self-biasing
differential input
Differential signal from DP source. DP1_P makes a differential pair with DP1_N.
The input to this pin must be AC-coupled externally.
DP1_N 8 self-biasing
differential input
Differential signal from DP source. DP1_N makes a differential pair with DP1_P.
The input to this pin must be AC-coupled externally.
AUX_P 2 self-biasing
differential I/O
Differential signal towards DP source. AUX_P makes a differential pair with
AUX_N. The pin must be AC-coupled externally.
AUX_N 1 self-biasing
differential I/O
Differential signal towards DP source. AUX_N makes a differential pair with
AUX_P. The pin must be AC-coupled externally.
HPDRX 11 single-ended
3.3 V CMOS
output
Hot Plug Detect signal to DP source.
LVDS interface signals
LVSAE_P 41 LVDS output Even bus, Channel A differential signal to LVDS receiver. LVSAE_P makes a
differential pair with LVSAE_N.
LVSAE_N 42 LVDS output Even bus, Channel A differential signal to LVDS receiver. LVSAE_N makes a
differential pair with LVSAE_P.
LVSBE_P 39 LVDS output Even bus, Channel B differential signal to LVDS receiver. LVSBE_P makes a
differential pair with LVSBE_N.
LVSBE_N 40 LVDS output Even bus, Channel B differential signal to LVDS receiver. LVSBE_N makes a
differential pair with LVSBE_P.
LVSCE_P 36 LVDS output Even bus, Channel C differential signal to LVDS receiver. LVSCE_P makes a
differential pair with LVSCE_N.
LVSCE_N 37 LVDS output Even bus, Channel C differential signal to LVDS receiver. LVSCE_N makes a
differential pair with LVSCE_P.
LVSCKE_P 34 LVDS clock
output
Even bus, clock differential signal to LVDS receiver. LVSCKE_P makes a
differential pair with LVSCKE_N.
LVSCKE_N 35 LVDS clock
output
Even bus, clock differential signal to LVDS receiver. LVSCKE_N makes a
differential pair with LVSCKE_P.
LVSDE_P 31 LVDS output Even bus, Channel D differential signal to LVDS receiver. LVSDE_P makes a
differential pair with LVSDE_N.
LVSDE_N 32 LVDS output Even bus, Channel D differential signal to LVDS receiver. LVSDE_N makes a
differential pair with LVSDE_P.
LVSAO_P 53 LVDS output Odd bus, Channel A differential signal to LVDS receiver. LVSAO_P makes a
differential pair with LVSAO_N.
LVSAO_N 54 LVDS output Odd bus, Channel A differential signal to LVDS receiver. LVSAO_N makes a
differential pair with LVSAO_P.
LVSBO_P 51 LVDS output Odd bus, Channel B differential signal to LVDS receiver. LVSBO_P makes a
differential pair with LVSBO_N.
LVSBO_N 52 LVDS output Odd bus, Channel B differential signal to LVDS receiver. LVSBO_N makes a
differential pair with LVSBO_P.

PTN3460BS/F4Y

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Display Interface IC eDP to LVDS bridge IC
Lifecycle:
New from this manufacturer.
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