PTN3460 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 12 March 2014 13 of 32
NXP Semiconductors
PTN3460
eDP to LVDS bridge IC
8.3 System control and operation
With its combination of embedded microcontroller, non-volatile memory, DPCD AUX and
I
2
C-bus interfaces, PTN3460 delivers significant value for customer applications by
providing higher degree of control and programmability.
By default, all user controllable registers can be accessed through DPCD AUX interface.
This interface is always enabled. This AUX interface delivers seamless access of
PTN3460 registers to system/platform (GPU) firmware driver. Nevertheless, use of
I
2
C-bus interface for configuring PTN3460 is left to the choice of system integrator.
DEV_CFG (pin 12) sets up I
2
C-bus configuration mode:
• Pull-down resistor to GND — PTN3460 operates as I
2
C-bus slave, low address
(0x40h)
• Open — PTN3460 operates as I
2
C-bus slave, high address (0xC0h)
• Pull-up resistor to V
DD(3V3)
— PTN3460 operates as I
2
C-bus master capable of
reading from external EEPROM
8.3.1 Reset, power-down and power-on initialization
The device has a built-in reset circuitry that generates internal reset signal after power-on.
All the internal registers and state machines are initialized and the registers take default
values. In addition, PTN3460 has a dedicated control pin RST_N. This serves the same
purpose as power-on reset, but without power cycling of the device/platform.
PTN3460 starts up in a default condition after power-on or after RST_N is toggled from
LOW to HIGH. The configuration pins are sampled at power-on, or external reset, or when
returning from Deep Sleep.
PTN3460 goes into Deep power-saving when PD_N is LOW. This will trigger a
power-down sequence. To leave Deep power-saving state, the system needs to drive
PD_N back to HIGH. If PD_N pin is open, the device will not enter Deep power-saving
state. Once the device is in Deep power-saving condition, the HPDRX pin will go LOW
automatically and this can be used by the system to remove the 3.3 V supply, if required.
Remark: The device will not respect the Panel power-down sequence if PD_N is asserted
LOW while video is being streamed to the display. So the system is not supposed to
toggle PD_N and RST_N pins asynchronously while the LVDS output is streaming video
to the display panel, but instead follow the panel powering sequence as described in
Section 8.3.3
.
