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DAC1405D750HW-C18

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 10 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Clock inputs (CLKP and CLKN)
[2]
V
i
input voltage CLKN V
gpd
<50mV or
CLKP
C
[3]
825 - 1575 mV
V
idth
input differential threshold
voltage
V
gpd
< 50 mV C
[3]
100 - +100 mV
R
i
input resistance D - 10 - M
C
i
input capacitance D - 0.5 - pF
Clock outputs (SYNCP and SYNCN)
V
o(cm)
common-mode output
voltage
C-V
DDA(1V8)
0.3
-V
V
O(dif)
differential output voltage C - 1.2 - V
R
o
output resistance D - 80 -
Digital inputs (I0 to I13, Q0 to Q13)
V
IL
LOW-level input voltage C GNDIO - 0.8 V
V
IH
HIGH-level input voltage C 1.6 - V
DD(IO)(3V3)
V
I
IL
LOW-level input current V
IL
=0.8V I - 60 - A
I
IH
HIGH-level input current V
IH
=2.3V I - 80 - A
Digital inputs (SDO, SDIO, SCLK, SCS_N and RESET_N)
V
IL
LOW-level input voltage C GNDIO - 1.0 V
V
IH
HIGH-level input voltage C 2.3 - V
DD(IO)(3V3)
V
I
IL
LOW-level input current V
IL
=1.0V I - 20 - nA
I
IH
HIGH-level input current V
IH
=2.3V I - 20 - nA
Analog outputs (IOUTAP, IOUTAN, IOUTBP and IOUTBN)
I
O(fs)
full-scale output current register value = 00h C - 1.6 - mA
default register C - 20 - mA
V
O
output voltage compliance range C 1.8 - V
DDA(3V3)
V
R
o
output resistance D - 250 - k
C
o
output capacitance D - 3 - pF
E
O
offset error variation C - 6 - ppm/C
E
G
gain error variation C - 18 - ppm/C
Reference voltage output (GAPOUT)
V
O(ref)
reference output voltage T
amb
= 25 C I 1.24 1.29 1.34 V
V
O(ref)
reference output voltage
variation
C - 117 - ppm/C
I
O(ref)
reference output current external voltage 1.25 V D - 40 - A
Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN)
I
O(aux)
auxiliary output current differential outputs I - 2.2 - mA
V
O(aux)
auxiliary output voltage compliance range C 0 - 2 V
N
DAC(aux)mono
auxiliary DAC monotonicity guaranteed D - 10 - bit
Table 5. Characteristics …continued
V
DDA(1V8)
=V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
=V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together;
T
amb
=
40
Cto+85
C; typical values measured at T
amb
=25
C; R
L
= 50
differential; I
O(fs)
= 20 mA; PLL off unless
otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 11 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Input timing (see Figure 10)
f
data
data rate Dual-port mode input C - - 185 MHz
t
w(CLK)
CLK pulse width C 40 - 60 %
t
h(i)
input hold time C 1.6 - - ns
t
su(i)
input set-up time C 0.8 - - ns
SYNC signal
t
d
delay time f
SYNC
= f
s
/ 4 C - 0.21 - ns
f
SYNC
= f
s
/8 C - 0.3 - ns
variation C - 0.27 - ps/C
Output timing
f
s
sampling frequency C - - 750 Msps
t
s
settling time to 0.5 LSB D - 20 - ns
NCO frequency range
f
NCO
NCO frequency register values
00000000h D - 0 - MHz
FFFFFFFFh D - 740 - MHz
f
step
step frequency D - 0.172 - Hz
Low-power NCO frequency range
f
NCO
NCO frequency register values
00000000h D - 0 - MHz
F8000000h D - 716.875 - MHz
f
step
step frequency D - 23.125 - MHz
Dynamic performance
SFDR spurious-free dynamic
range
f
s
= 737.28 Msps
f
data
= 92.16 MHz; B = f
data
/2
f
o
= 4 MHz; 0 dBFS C - 77 - dBc
f
data
=184.32MHz; B=f
data
/2
f
o
=19MHz; 0dBFS I - 74 - dBc
f
o
=70MHz; 0dBFS C - 86 - dBc
SFDR
RBW
restricted bandwidth
spurious-free dynamic
range
f
o
=153.6MHz; 0dBFS; f
data
= 184.32 MHz; f
s
= 737.28 Msps
B = 20 MHz C - 86 - dBc
B=100MHz C - 80.5 - dBc
B = 20 MHz; 8-tone;
500 kHz spacing
C-76- dBc
Table 5. Characteristics
…continued
V
DDA(1V8)
=V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
=V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together;
T
amb
=
40
Cto+85
C; typical values measured at T
amb
=25
C; R
L
= 50
differential; I
O(fs)
= 20 mA; PLL off unless
otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 12 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.
[2] CLKP and CLKN inputs are at differential LVDS levels. An external differential resistor with a value of between 80 and 120 should
be connected across the pins (see Figure 8).
[3] V
gpd
represents the ground potential difference voltage. This is the voltage that results from current flowing through the finite resistance
and the inductance between the receiver and the driver circuit ground voltages.
[4] IMD3 rejection with 6 dBFS/tone.
IMD3 third-order intermodulation
distortion
f
data
=184.32MHz; f
s
= 737.28 Msps
f
o1
=95MHz;
f
o2
=97MHz
C
[4]
-77 - dBc
f
o1
= 137 MHz;
f
o2
= 143 MHz
C
[4]
-74 - dBc
f
o1
= 152.5 MHz;
f
o2
= 153.5 MHz
I
[4]
-74 - dBc
ACPR adjacent channel power
ratio
f
data
=184.32MHz; f
s
= 737.28 Msps; f
o
=96MHz
1-carrier; B = 5 MHz I - 75 - dBc
2-carrier; B = 10 MHz C - 72 - dBc
4-carrier; B = 20 MHz C - 68.5 - dBc
f
data
=184.32MHz; f
s
= 737.28 Msps; f
o
=153.6MHz
1-carrier; B = 5 MHz C - 73 - dBc
2-carrier; B = 10 MHz C - 71 - dBc
4-carrier; B = 20 MHz C - 67 - dBc
NSD noise spectral density
f
data
=184.32MHz; f
s
= 737.28 Msps
f
o
=19MHz;0dBFS C - 161 - dBFS/Hz
f
o
= 153.6 MHz;
0 dBFS;
C-156 - dBFS/Hz
f
o
= 153.6 MHz;
10 dBFS
C-158 - dBFS/Hz
Table 5. Characteristics
…continued
V
DDA(1V8)
=V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
=V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together;
T
amb
=
40
Cto+85
C; typical values measured at T
amb
=25
C; R
L
= 50
differential; I
O(fs)
= 20 mA; PLL off unless
otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit
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DAC1405D750HW-C18

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IC DAC 14BIT A-OUT 100HTQFP
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