DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 25 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.5.1 Timing when using the internal PLL (PLL on)
In Table 33 the links between internal and external clocking are defined. The setting
applied to PLL_DIV[1:0] (register 02h[4:3]; see Table 9 “Register allocation map”) allows
the frequency between the digital part and the DAC core to be adjusted.
The settings applied to DAC_CLK_DELAY[1:0] (register 02h[2:1]) and DAC_CLK_POL
(register 02h[0]), allow adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in Table 34.
10.5.2 Timing when using an external PLL (PLL off)
It is recommended that a delay of 280 ps is used on the internal digital clock (CLK
dig
) to
obtain optimum device performance up to750 Msps.
10.6 FIR filters
The DAC1405D750 integrates three selectable Finite Impulse Response (FIR) filters
which enables the device to use 4 or 8 interpolation rates. All three interpolation filters
have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than
0.0005 dB. The coefficients of the interpolation filters are given in Table 36.
Fig 10. Input timing diagram when internal PLL bypassed (off)
001aal384
N
t
su(i)
90 %
50 %
90 %
I13 to I0/
Q13 to Q0
SYNC
(SYNCP − SYNCN)
t
h(i)
N + 1 N + 2
Table 33. Frequencies
Mode CLK input
(MHz)
Input data rate
(MHz)
Interpolation Update rate
(Msps)
PLL_DIV[1:0]
Dual Port 185 185 4 740 01 (/ 4)
Dual Port 92.5 92.5 8 740 10 (/ 8)
Interleaved 370 370 4 740 00 (/ 2)
Interleaved 185 185 8 740 01 (/ 4)
Table 34. Sample clock phase and polarity examples
Mode Input data rate
(MHz)
Interpolation Update rate
(Msps)
DAC_CLK_
DELAY [1:0]
DAC_CLK_
POL
Dual Port 92.5 4 370 01 0
Dual Port 92.5 8 740 01 0
Table 35. Optimum external PLL timing settings
Address Register name Value
Dec Hex Digital clock delay Bin Dec Hex
2 02h PLLCFG 280 ps 10001000 136 88h
