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DAC1405D750HW-C18

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 28 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.9 DAC transfer function
The full-scale output current for each DAC is the sum of the two complementary current
outputs:
(3)
The output current depends on the digital input data:
(4)
(5)
The setting applied to CODING (register 00h[2]; see Table 9 “Register allocation map”)
defines whether the DAC1405D750 operates with a binary input or a two’s complement
input.
Table 38 shows the output current as a function of the input data, when I
O(fs)
= 20 mA.
10.10 Full-scale current
10.10.1 Regulation
The DAC1405D750 reference circuitry integrates an internal bandgap reference voltage
which delivers a 1.29 V reference to the GAPOUT pin. It is recommended to decouple pin
GAPOUT using a 100 nF capacitor.
The reference current is generated via an external resistor of 953 (1 %) connected to
pin VIRES. A control amplifier sets the appropriate full-scale output current (I
O(fs)
) for both
DACs (see Figure 11).
Table 38. DAC transfer function
Data I13 to I0 and Q13 to Q0 IOUTP (mA) IOUTN (mA)
Binary Two’s complement
0 00 0000 0000 0000 10 0000 0000 0000 0 20
... ... ... ... ...
8192 10 0000 0000 0000 00 0000 0000 0000 10 10
... ... ... ... ...
16383 11 1111 1111 1111 01 1111 1111 1111 20 0
I
Ofs
I
IOUTP
I
IOUTN
+=
I
IOUTP
I
Ofs
DATA
16383
----------------


=
I
IOUTN
I
Ofs
16383 DATA–
16383
-------------------------------------


=
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 29 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
This configuration is optimum for temperature drift compensation because the bandgap
reference voltage can be matched to the voltage across the feedback resistor.
The DAC current can also be set by applying an external reference voltage to the
non-inverting input pin GAPOUT and disabling the internal bandgap reference voltage
with GAP_PD (register 00h[0]; see Table 10 “COMMon register (address 00h) bit
description”).
10.10.2 Full-scale current adjustment
The default full-scale current (I
O(fs)
) is 20 mA but further adjustments can be made by the
user to both DACs independently via the serial interface from 1.6 mA to 22 mA, 10 %.
The settings applied to DAC_A_GAIN_COARSE[3:0] (see Table 20 “DAC_A_Cfg_2
register (address 0Ah) bit description” and Table 21 “DAC_A_Cfg_3 register (address
0Bh) bit description”) and to DAC_B_GAIN COARSE[3:0] (see Table 23 “DAC_B_Cfg_2
register (address 0Dh) bit description” and Table 24 “DAC_B_Cfg_3 register (address
0Eh) bit description”) define the coarse variation of the full-scale current (see Table 39).
Fig 11. Internal reference configuration
aaa-002266
REF.
BANDGAP
GAPOUT
V
DDA(1V8)
VIRES
DAC
CURRENT
SOURCES
ARRAY
AGND
AGND
100 nF
953 Ω
(1 %)
100
kΩ
Table 39. I
O(fs)
coarse adjustment
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0] I
O(fs)
(mA)
Decimal Binary
0 0000 1.6
1 0001 3.0
2 0010 4.4
3 0011 5.8
4 0100 7.2
5 0101 8.6
6011010.0
7 0111 11.4
8 1000 12.8
9 1001 14.2
10 1010 15.6
11 1011 17.0
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 30 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
The settings applied to DAC_A_GAIN_FINE[5:0] (see Table 20 “DAC_A_Cfg_2 register
(address 0Ah) bit description”) and to DAC_B_GAIN_FINE[5:0] (see Table 23
“DAC_B_Cfg_2 register (address 0Dh) bit description”) define the fine variation of the
full-scale current (see Table 40).
The coding of the fine gain adjustment is two’s complement.
10.11 Digital offset adjustment
When the DAC1405D750 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common-mode level at the output of the DAC.
It adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (see Table 19 “DAC_A_Cfg_1 register
(address 09h) bit description” and Table 21 “DAC_A_Cfg_3 register (address 0Bh) bit
description”) and to “DAC_B_OFFSET[11:0]” (see Table 22 “DAC_B_Cfg_1 register
(address 0Ch) bit description” and Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit
description”) define the range of variation of the digital offset (see Table 41).
12 1100 18.5
13 1101 20.0
14 1110 21.0
15 1111 22.0
Table 40. I
O(fs)
fine adjustment
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0] Delta I
O(fs)
Decimal Two’s complement
32 10 0000 10.3 %
... ... ...
0 00 0000 0
... ... ...
31 01 1111 +10 %
Table 39. I
O(fs)
coarse adjustment …continued
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0] I
O(fs)
(mA)
Decimal Binary
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DAC1405D750HW-C18

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IC DAC 14BIT A-OUT 100HTQFP
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