DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 19 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Table 14. FREQNCO_LISB register (address 04h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[15:8] R/W - lower intermediate 8 bits for the NCO
frequency setting
Table 15. FREQNCO_UISB register (address 05h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[23:16] R/W - upper intermediate 8 bits for the NCO
frequency setting
Table 16. FREQNCO_MSB register (address 06h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[31:24] R/W - most significant 8 bits for the NCO frequency
setting
Table 17. PHINCO_LSB register (address 07h) bit description
Bit Symbol Access Value Description
7 to 0 PH_NCO[7:0] R/W - lower 8 bits for the NCO phase setting
Table 18. PHINCO_MSB register (address 08h) bit description
Bit Symbol Access Value Description
7 to 0 PH_NCO[15:8] R/W - most significant 8 bits for the NCO phase
setting
Table 19. DAC_A_Cfg_1 register (address 09h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 DAC_A_PD R/W DAC A power
0on
1off
6 DAC_A_SLEEP R/W DAC A Sleep mode
0disabled
1 enabled
5 to 0 DAC_A_OFFSET[5:0] R/W - lower 6 bits for the DAC A offset
Table 20. DAC_A_Cfg_2 register (address 0Ah) bit description
Bit Symbol Access Value Description
7 to 6 DAC_A_GAIN_
COARSE[1:0]
R/W - lower 2 bits for the DAC A gain setting for
coarse adjustment
5 to 0 DAC_A_GAIN_
FINE[5:0]
R/W - lower 6 bits for the DAC A gain setting for fine
adjustment
