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DAC1405D750HW-C18

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 22 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.2.5 Recommended configuration
It is recommended that the following additional settings are used to obtain optimum
performance at up to 750 Msps.
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines
whether the DAC1405D750 operates in the Dual-port mode or in Interleaved mode (see
Table 32).
10.3.1 Dual-port mode
The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
Table 31. Recommended configuration
Address Value
Dec Hex Bin Dec Hex
17 11h 00001010 10 0Ah
19 13h 01101100 108 6Ch
20 14h 01101100 108 6Ch
Table 32. Mode selection
Bit 3 setting Function I13 to I0 Q13 to Q0 Pin 41
0 Dual port mode active active Q13
1 Interleaved mode active off SELIQ
Fig 5. Dual-port mode
001aal653
LATCH
I
2 × 2 × 2 ×
I13 to I0
FIR 1
FIR 1
FIR 2
FIR 2
FIR 3
FIR 3
LATCH
Q
2 × 2 × 2 ×
Q13 to Q0
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 23 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.3.2 Interleaved mode
The data input for the Interleaved mode operation is illustrated in Figure 6.
In Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal.
The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and
Q channels; see Figure 7.
The SELIQ signal can be either synchronous or asynchronous (single rising edge, single
pulse). The first data following the SELIQ rising edge is sent in channel I and following
data is sent in channel Q. After this, data is distributed alternately between these
channels.
Fig 6. Interleaved mode operation
CLK
dig
= internal digital clock
Fig 7. Interleaved mode timing (8x interpolation, latch on rising edge)
001aaj814
NIn
SELIQ
(synchronous alternative)
SELIQ
(asynchronous alternative 1)
SELIQ
(asynchronous alternative 2)
CLK
dig
Latch I output
Latch Q output
XX N N + 2
N + 1 N + 2 N + 3 N + 4 N + 5
XX N + 1 N + 3
DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 24 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.4 Input clock
The DAC1405D750 can operate at the following clock frequencies:
PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off: up to 750 MHz
The input clock is LVDS compliant (see Figure 8) but it can also be interfaced with CML
differential sine wave signal (see Figure 9).
10.5 Timing
The DAC1405D750 can operate at a sampling frequency (f
s
) up to 750 Msps with an input
data rate (f
data
) up to 185 MHz. When using the internal PLL, the input data is referenced
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in Figure 10.
Fig 8. LVDS clock configuration
Fig 9. Interfacing CML to LVDS
001aah021
100 Ω
LVDS
CLKINP
CLKINN
LVDS
Z
diff
= 100 Ω
001aah020
55 Ω
55 Ω
1.1 kΩ
2.2 kΩ
100 nF
CML
100 nF
100 nF
CLKINP
LVDS
CLKINN
AGND
V
DDA(1V8)
1 kΩZ
diff
= 100 Ω
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DAC1405D750HW-C18

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IC DAC 14BIT A-OUT 100HTQFP
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