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DAC1405D750 6 © IDT 2012. All rights reserved.
Product data sheet Rev. 06 — 2 July 2012 16 of 41
Integrated Device Technology
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Table 9. Register allocation map
Address Register name R/W Bit definition Default
Dec Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bin Dec Hex
0 00h COMMon R/W 3W_SPI SPI_RST CLK_SEL - MODE_
SEL
CODING IC_PD GAP_PD 10000000 128 80
1 01h TXCFG R/W NCO_ON NCO_LP_
SEL
INV_SIN_
SEL
MODULATION[2:0] INTERPOLATION[1:0] 10000111 135 87
2 02h PLLCFG R/W PLL_PD - PLL_DIV_
PD
PLL_DIV[1:0] DAC_CLK_DELAY[1:0] DAC_CLK
_POL
00010000 16 10
3 03h FREQNCO_LSB R/W FREQ_NCO[7:0] 01100110 102 66
4 04h FREQNCO_LISB R/W FREQ_NCO[15:8] 01100110 102 66
5 05h FREQNCO_UISB R/W FREQ_NCO[23:16] 01100110 102 66
6 06h FREQNCO_MSB R/W FREQ_NCO[31:24] 00100110 38 26
7 07h PHINCO_LSB R/W PH_NCO[7:0] 00000000 0 00
8 08h PHINCO_MSB R/W PH_NCO[15:8] 00000000 0 00
9 09h DAC_A_Cfg_1 R/W DAC_A_PD DAC_A_
SLEEP
DAC_A_OFFSET[5:0] 00000000 0 00
10 0Ah DAC_A_Cfg_2 R/W DAC_A_GAIN_
COARSE[1:0]
DAC_A_GAIN_FINE[5:0] 01000000 64 40
11 0Bh DAC_A_Cfg_3 R/W DAC_A_GAIN_
COARSE[3:2]
DAC_A_OFFSET[11:6] 11000000 192 C0
12 0Ch DAC_B_Cfg_1 R/W DAC_B_PD DAC_B_
SLEEP
DAC_B_OFFSET[5:0] 00000000 0 00
13 0Dh DAC_B_Cfg_2 R/W DAC_B_GAIN_
COARSE[1:0]
DAC_B_GAIN_FINE[5:0] 01000000 64 40
14 0Eh DAC_B_Cfg_3 R/W DAC_B_GAIN_
COARSE[3:2]
DAC_B_OFFSET[11:6] 11000000 192 C0
15 0Fh DAC_Cfg R/W - MINUS_
3DB
NOISE_
SHPER
00000000 0 00
16 10h SYNC_Cfg R/W SYNC_DIV SYNC_SEL - 00000000 0 00
26 1Ah DAC_A_Aux_MSB R/W AUX_A[9:2] 10000000 128 80
27 1Bh DAC_A_Aux_LSB R/W AUX_A_PD - AUX_A[1:0] 00000000 0 00
28 1Ch DAC_B_Aux_MSB R/W AUX_B[9:2] 10000000 128 80
29 1Dh DAC_B_Aux_LSB R/W AUX_B_PD - AUX_B[1:0] 00000000 0 00
