PCA9555 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 8 November 2017 11 of 34
NXP Semiconductors
PCA9555
16-bit I
2
C-bus and SMBus I/O port with interrupt
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must first send the PCA9555
address with the least significant bit set to a logic 0 (see Figure 7 “
PCA9555 device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte will
then be sent by the PCA9555 (see Figure 11
, Figure 12 and Figure 13). Data is clocked
into the register on the falling edge of the acknowledge clock pulse. After the first byte is
read, additional bytes may be read but the data will now reflect the information in the other
register in the pair. For example, if you read Input Port 1, then the next byte read would be
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the final byte received, the bus master must not acknowledge the data.
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 11. Read from register
AS
START condition R/W
acknowledge
from slave
002aac222
A
acknowledge
from slave
SDA
A P
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 0 0 A2 A1 A0 1 A0
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
COMMAND BYTE
1 0 0 A2 A1 A00 0
data from lower or
upper byte of register
LSBMSB
DATA (last byte)
data from upper or
lower byte of register
LSBMSB
