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PCA9698BS,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 13 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.5 MSK0 to MSK4 - Mask interrupt registers
These registers mask the interrupt due to a change in the I/O pins configured as inputs.
‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).
Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).
7.4.6 OUTCONF - output structure configuration register
This register controls the configuration of the output ports as open-drain or totem-pole.
The 4 least significant bits control the output architecture for bank 0, 2 bits at a time.
OUT001 controls the output structure for IO0_0 and IO0_1
OUT023 controls the output structure for IO0_2 and IO0_3
OUT045 controls the output structure for IO0_4 and IO0_5
OUT067 controls the output structure for IO0_6 and IO0_7
The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit
controlling one bank.
OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)
OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7)
OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7)
OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7)
OUTx = 0: The I/Os are configured with an open-drain structure.
OUTx = 1: The I/Os are configured with a totem-pole structure.
Table 8. MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
20h MSK0 7 to 0 M0[7:0] R/W 1111 1111* Mask Interrupt register bank 0
21h MSK1 7 to 0 M1[7:0] R/W 1111 1111* Mask Interrupt register bank 1
22h MSK2 7 to 0 M2[7:0] R/W 1111 1111* Mask Interrupt register bank 2
23h MSK3 7 to 0 M3[7:0] R/W 1111 1111* Mask Interrupt register bank 3
24h MSK4 7 to 0 M4[7:0] R/W 1111 1111* Mask Interrupt register bank 4
Table 9. OUTCONF - output structure configuration register (address 28h) description
Bit 7 6 5 4 3 2 1 0
Symbol OUT4 OUT3 OUT2 OUT1 OUT067 OUT045 OUT023 OUT001
Default 11111111
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 14 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.4.7 ALLBNK - All Bank control register
This register allows all the I/Os configured as outputs to be programmed with the same
logic value. This programming is applied to all the banks or a selection of banks.
When this register is programmed, values in the Output Port registers are not changed
and do not reflect the states of I/Os configured as outputs anymore.
• B0 to B4 controls the logic level to be applied to Bank 0 to Bank 4, respectively.
– Bx = 0: All the I/Os configured as outputs in the corresponding Bank x are
programmed with 0s.
– Bx = 1: All the I/Os configured as outputs in the corresponding Bank x are
programmed with 1s.
• Bit 5 and bit 6 are not used and can be programmed to either ‘1’ or ‘0’.
• BSEL is a filter bit that allows programming of some banks only, and not the others.
– BSEL = 0:
When Bx = 0, all the I/Os configured as output in the corresponding Bank x are
programmed with 0s.
When Bx = 1, all the I/Os configured as output in the corresponding Bank x are
programmed with their actual value from the corresponding output register.
– BSEL = 1:
When Bx = 0, all the I/Os configured as output in the corresponding Bank x are
programmed with their actual value from the corresponding output register.
When Bx = 1, all the I/Os configured as output in the corresponding Bank x are
programmed with 1s.
7.4.7.1 Examples
• If ALLBNK = 0XX0 0000:
All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 0s,
overwriting values programmed in the five Output Port registers.
• If ALLBNK = 1XX1 1111:
All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 1s,
overwriting values programmed in the five Output Port registers.
• If ALLBNK = 0XX0 0110:
All I/Os configured as outputs in Banks 0, 3, and 4 only will be programmed with 0s,
overwriting values programmed in the Output Port registers 0, 3, and 4, while I/Os
configured as outputs in Bank 1 and Bank 2 are programmed with values in Output
Port registers 1 and 2.
Table 10. ALLBNK - All Bank control register (address 29h) description
Bit 7 6 5 4 3 2 1 0
Symbol BSEL X X B4 B3 B2 B1 B0
Default 10000000
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 15 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
• If ALLBNK = 1XX0 1100:
All I/Os configured as outputs in Bank 2 and 3 will be programmed with 1s, overwriting
values programmed in the Output Port registers 2 and 3, while I/Os configured as
outputs in Bank 0, 1, and 4 are programmed with values in Output Port registers 0, 1,
and 4.
7.4.8 MODE - PCA9698 mode selection register
This register allows programming of the PCA9698 modes.
• OEPOL bit controls the polarity of OE pin.
– OEPOL = 0: OE
pin is active LOW.
– OEPOL = 1: OE
pin is active HIGH (equivalent to OE pin).
• OCH bit selects the I
2
C-bus event where the state of the I/Os configured as outputs
change.
– OCH = 0: outputs change on STOP command.
– OCH = 1: outputs change on ACK.
• IOAC bit controls the ability of the device to respond to a ‘GPIO All Call’ command
(see Section 7.6 “
GPIO All Call” for more information), allowing programming of more
than one device at the same time.
– IOAC = 0: The device cannot respond to a ‘GPIO All Call’ command.
– IOAC = 1: The device can respond to a ‘GPIO All Call’ command.
Remark: The ‘GPIO ALL CALL’ command defined for the PCA9698 is different from
the I
2
C-bus protocol ‘General Call’ command.
• SMBA bit controls the capability of the PCA9698 to respond to a SMBAlert command.
– SMBA = 0: PCA9698 does not respond to an Alert Response Address.
– SMBA = 1: PCA9698 responds to an Alert Response Address. Bits 5, 6 and 7 are
reserved and must be programmed with 0s.
• Unused bits (bits 2, 5, 6 and 7) must be programmed with 0s for proper device
operation.
Table 11. MODE - mode selection register (address 2Ah) description
Bit 7 6 5 4 3 2 1 0
Symbol X X X SMBA IOAC X OCH OEPOL
Default 00000010
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

PCA9698BS,118

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Buy PCA9698BS,118
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders I2C I/O EXPANDER GP
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