PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 25 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
8.4 Bus transactions
Data is transmitted to the PCA9698 registers using ‘Write Byte’ transfers (see Figure 15,
Figure 16
, Figure 17, and Figure 18).
Data is read from the PCA9698 registers using ‘Read Byte’ and ‘Receive Byte’ transfers
(see Figure 19
and Figure 20).
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PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 26 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs.
If more than 5 bytes are written, previous data are overwritten.
Fig 15. Write to the 5 output ports
002aab94
4
S
1 0 0 0 1 0 0 0
A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
command register
AI = 1
Output Port
register bank 0
is selected
A
acknowledge
from slave
DATA BANK 0
A
acknowledge
from slave
DATA BANK 1
acknowledge
from slave
A
acknowledge
from slave
DATA BANK 2
A
acknowledge
from slave
DATA BANK 3
A
acknowledge
from slave
DATA BANK 4
P
STOP
condition
A
acknowledge
from slave
SDA
t
v(Q)
write to port when OCH = 0
data out from port when OCH = 0
write to port when OCH = 1
data out from port when OCH = 1
data valid
all banks
data valid
bank 0
data valid
bank 1
data valid
bank 2
data valid
bank 3
data valid
bank 4
t
v(Q)
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 27 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs.
OCH = 0. When OCH = 1, the change in the port happens at the acknowledge phase.
Two, three, or four adjacent banks can be programmed by using the Auto-Increment feature (AI = 1) and change at the
corresponding output port becomes effective at the STOP command when OCH = 0, or at each acknowledge when OCH = 1.
Fig 16. Write to a specific output port
002aab94
5
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
A
acknowledge
from slave
DATA BANK X
P
STOP
condition
ASDA
t
v(Q)
write to port
data out from port
data X valid
AI0001D2D1D0
acknowledge
from slave
acknowledge
from slave
bank X
determined by
D2, D1, D0
The programing becomes effective at the Acknowledge.
Less than 5 bytes can be programmed by using the same scheme. ‘D5 D4 D3 D2 D1 D0’ refers to the first register to be
programmed.
If more than 5 bytes are written, previous data are overwritten (the sixth configuration register will roll over to the first addressed
configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register, the sixth
Mask interrupt register will roll over to the first addressed Mask interrupt register.
Fig 17. Write to the I/O Configuration, Polarity Inversion, or Mask interrupt registers (5 banks)
002aab946
S A6 A5 A4 A3 A2 A1 A0 0 A
slave address
R/W
START condition
command register
AI = 1
A
acknowledge
from slave
DATA BANK 0
A
acknowledge
from slave
DATA BANK 1
acknowledge
from slave
A
acknowledge
from slave
DATA BANK 2
A
acknowledge
from slave
DATA BANK 3
A
acknowledge
from slave
DATA BANK 4
P
STOP
condition
A
SDA
1 0 D5 D4 D3 D2 D1 D0
01 0000 for Polarity Inversion register programming bank 0
01 1000 for Configuration register programming bank 0
10 0000 for Mask interrupt register programming bank 0
acknowledge
from slave

PCA9698BS,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders I2C I/O EXPANDER GP
Lifecycle:
New from this manufacturer.
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