PCA9698BS,118 Datasheet PCA9698BS,118, PCA9698DGG,512, PCA9698DGG,518 | P7-P9

Product data sheet Rev. 3 — 3 August 2010 7 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

C-bus advanced I/O port with RESET, OE and INT

[1] HVQFN56 package die supply ground is connected to both V

pins and exposed center pad. V

pins

must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board and for proper heat conduction through the board, thermal vias need to be

incorporated in the printed-circuit board in the thermal pad region.

7. Functional description

Refer to Figure 1 “Block diagram of PCA9698”.

7.1 Device address

Following a START condition the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address of the

PCA9698 is shown in Figure 5

. Slave address pins AD2, AD1 and AD0 choose 1 of

64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on

AD2, AD1 and AD0. Address values depending on AD2, AD1 and AD0 can be found in

Table 12 “

PCA9698 address map”.

The last bit of the first byte defines the operation to be performed. When set to logic 1 a

read is selected while a logic 0 selects a write operation.

AD2 29 22 input address input 2

30 23 input active LOW output enable

INT

/SMBALERT 55 48 output active LOW interrupt output/

active LOW SMBus alert

output

RESET

56 49 input active LOW reset input

Table 2. Pin description

…continued

Symbol Pin Type Description

TSSOP56 HVQFN56

Fig 5. PCA9698 device address

R/W

002aab93

A6 A5 A4 A3 A2 A1 A0

programmable

slave address

Product data sheet Rev. 3 — 3 August 2010 8 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

C-bus advanced I/O port with RESET, OE and INT

7.2 Alert response, GPIO All Call and Device ID addresses

Three other different addresses can be sent to the PCA9698.

• Alert Response address: allows to perform an ‘SMBus Alert’ operation as defined in

the SMBus specification. This address is always used to perform a Read operation.

See Section 7.11 “

SMBus Alert output (SMBALERT)” for more information.

• GPIO All Call address: allows to program several Advanced GPIO devices at the

same time. This address is always used to perform a Write operation. See Section 7.6

“GPIO All Call” for more information.

• Device ID address: allows to read ID information from the device (manufacturer, part

identification, revision). See Section 7.5 “

Device ID - PCA9698 ID field” for more

information.

7.3 Command register

Following the successful acknowledgement of the slave address + R/W bit, the bus

master will send a byte to the PCA9698, which will be stored in the Command register.

The lowest 6 bits are used as a pointer to determine which register will be accessed.

Registers are divided into 2 categories: 5-bank register category, and 1-bank register

category.

Only a command register code with the 7 least significant bits equal to the 28 allowable

values as defined in Table 3 “

undefined command codes will not be acknowledged. At power-up, this register defaults

to 80h, with the AI bit set to ‘1’, and the lowest 7 bits set to ‘0'.

During a write operation, the PCA9698 will acknowledge a byte sent to the OP, PI, IOC,

MSK, OUTCONF, ALLBNK, and MODE registers, but will not acknowledge a byte sent to

the IPx registers since these are read-only registers.

Fig 6. Alert Response address Fig 7. GPIO All Call address Fig 8. Device ID address

002aab93

0 0 0 1 1 0 0

R/W

002aab93

1 1 0 1 1 1 0 0

R/W

002aab94

1 1 1 1 1 0 0

Fig 9. Command register

002aab94

1 0 0 0 0 0 0

D0AI − D5 D4 D3 D2 D1

Auto-Increment

default at power-up

or after RESET

Product data sheet Rev. 3 — 3 August 2010 9 of 48

NXP Semiconductors

PCA9698

40-bit Fm+ I

C-bus advanced I/O port with RESET, OE and INT

7.3.1 5-bank register category

• IP – Input registers

• OP – Output registers

• PI – Polarity Inversion registers

• IOC – I/O Configuration registers

• MSK – Mask interrupt registers

If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically

incremented after a read or write. This allows the user to program and/or read the

5 register banks sequentially.

If more than 5 bytes of data are written and AI = 1, previous data in the selected registers

will be overwritten or reread. Reserved registers are skipped and not accessed (refer to

Table 3

If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not

incremented after data is read or written, only one register will be repeatedly read or

written.

7.3.2 1-bank register category

• OUTCONF – Output Structure Configuration register

• ALLBNK – All Bank Control register

• MODE – Mode Selection register

If more than 1 byte of data is written or read, previous data in the same register is

overwritten independently of the value of AI.

7.4 Register definitions

Table 3. Register summary

Reg # D5 D4 D3 D2 D1 D0 Name Type Function

Input Port registers

00h 0 0 0 0 0 0 IP0 read only Input Port register bank 0

01h 0 0 0 0 0 1 IP1 read only Input Port register bank 1

02h 0 0 0 0 1 0 IP2 read only Input Port register bank 2

03h 0 0 0 0 1 1 IP3 read only Input Port register bank 3

04h 0 0 0 1 0 0 IP4 read only Input Port register bank 4

05h 0 0 0 1 0 1 - - reserved for future use

06h 0 0 0 1 1 0 - - reserved for future use

07h 0 0 0 1 1 1 - - reserved for future use

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P42 P43-P45 P46-P48

PCA9698BS,118

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PCA9698BS,118

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