PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 19 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.11 SMBus Alert output (SMBALERT)
The interrupt output pin (INT) can also be used as an Alert line (SMBALERT).
The SMBALERT
pins of multiple devices with this feature can be connected together to
form a wired-AND signal and can be used in conjunction with the SMBus Alert Response
Address. ‘SMBus Alert’ message is 2 bytes long and allows the master to determine
which device generated the Alert (SMBALERT
going LOW).
When SMBA bit = 1 (register 2Ah, bit 4), the PCA9698 supports the SMBus Alert function
and its INT
/SMBALERT pin may be connected as an SMBus Alert signal.
When a master device senses that an ‘SMBus Alert’ condition is present on the ALERT
line (SMBALERT
pin of the PCA9698 and/or other devices going LOW):
It accesses the slave device(s) through the Alert Response Address (ARA)
associated with a Read Command: Start 0001 100 + R/W
=1.
If the PCA9698 is the device that generated the ‘SMBus Alert’ condition (and its
SMBA bit = 1), it will acknowledge the SMBus Alert command and respond by
transmitting its slave address on the SDA line. The 8
th
bit (LSB) of the slave address
byte will be a zero.
The device will acknowledge an ARA command only if the SMBALERT signal has
been previously asserted (SMBALERT
= LOW).
If more than one device pulls its SMBALERT pin LOW, the highest priority (lowest
I
2
C-bus address) device will win communication rights via standard I
2
C-bus arbitration
during the slave address transfer.
If the PCA9698 wins the arbitration, its SMBALERT pin will become inactive (will go
HIGH) at the completion of the slave address transmission (9
th
clock pulse, NACK
phase).
If the PCA9698 loses the arbitration, its SMBALERT pin will remain active (will stay
LOW).
The master ends the sequence by sending a NACK and then STOP command.
If the SMBALERT is still LOW after transfer is complete, it means that more than one
device made the request. Another full transaction is then required.
Remark: If the master initiates an ‘SMBus Alert’ sequence with a Write Command, none
of the slave devices acknowledge. The SMBALERT
is open-drain and requires a pull-up
resistor to V
DD
.
Remark: If the master sends an ACK after reading the I
2
C-bus slave address, the slave
device keeps sending ‘1’s until a NACK is received.
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 20 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.12 Output enable input (OE)
The configurable active LOW or active HIGH output enable pin allows to enable or disable
all the I/Os at the same time.
When a LOW level is applied to the OE pin, with OEPOL = 0 (register 2Ah, bit 4) or a
HIGH level is applied to the OE
pin, with OEPOL = 1 (register 2Ah, bit 0), all the I/Os
configured as outputs are enabled and the logic value programmed in their respective
OP registers is applied to the pins.
When a HIGH level is applied to the OE pin, with OEPOL = 0 (register 2Ah, bit 0) or a
LOW level is applied to the OE
pin, with OEPOL = 1 (register 2Ah, bit 0), all the I/Os
configured as outputs are 3-stated.
For applications requiring LED blinking with brightness control, this pin can be used to
control the brightness by applying a high frequency PWM signal on the OE
pin. LEDs can
be blinked using the Output Port registers and can be dimmed using the PWM signal on
the OE
pin thus controlling the brightness by adjusting the duty cycle.
Default is OEPOL = 0, so if the OE
pin is held HIGH, the outputs are disabled. The OE pin
needs to be pulled LOW or OEPOL changed to ‘1’ to enable the outputs.
It is recommended to define the required polarity of the OE
input by programing the value
of OEPOL before programming the configuration registers (IOC register).
7.13 Live insertion
The PCA9698 is fully specified for live-insertion applications using I
OFF
, power-up
3-states, robust state machine, and 50 ns noise filter. The I
OFF
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-states circuitry places the outputs in the high-impedance state
during power-up and power-down, which prevents driver conflict and bus contention.
The robust state machine does not respond until it sees a valid START condition and the
50 ns noise filter will filter out any insertion glitches. The PCA9698 will not cause
corruption of active data on the bus nor will the device be damaged or cause damage to
devices already on the bus when similar featured devices are being used.
7.14 Standby
The PCA9698 goes into standby when the I
2
C-bus is idle. Standby supply current is lower
than 1.0 μA (typical).
PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 21 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
7.15 Address map
Table 12. PCA9698 address map
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 Address
V
SS
SCL V
SS
001000020h
V
SS
SCL V
DD
001000122h
V
SS
SDA V
SS
001001024h
V
SS
SDA V
DD
001001126h
V
DD
SCL V
SS
001010028h
V
DD
SCL V
DD
00101012Ah
V
DD
SDA V
SS
00101102Ch
V
DD
SDA V
DD
00101112Eh
V
SS
SCLSCL001100030h
V
SS
SCLSDA001100132h
V
SS
SDASCL001101034h
V
SS
SDASDA001101136h
V
DD
SCLSCL001110038h
V
DD
SCLSDA00111013Ah
V
DD
SDASCL00111103Ch
V
DD
SDASDA00111113Eh
V
SS
V
SS
V
SS
010000040h
V
SS
V
SS
V
DD
010000142h
V
SS
V
DD
V
SS
010001044h
V
SS
V
DD
V
DD
010001146h
V
DD
V
SS
V
SS
010010048h
V
DD
V
SS
V
DD
01001014Ah
V
DD
V
DD
V
SS
01001104Ch
V
DD
V
DD
V
DD
01001114Eh
V
SS
V
SS
SCL010100050h
V
SS
V
SS
SDA010100152h
V
SS
V
DD
SCL010101054h
V
SS
V
DD
SDA010101156h
V
DD
V
SS
SCL010110058h
V
DD
V
SS
SDA01011015Ah
V
DD
V
DD
SCL01011105Ch
V
DD
V
DD
SDA01011115Eh

PCA9698BS,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders I2C I/O EXPANDER GP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union