PCA9698 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 3 — 3 August 2010 37 of 48
NXP Semiconductors
PCA9698
40-bit Fm+ I
2
C-bus advanced I/O port with RESET, OE and INT
12. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
Table 15. Dynamic characteristics
Symbol Parameter Conditions Standard-mode
I
2
C-bus
Fast-mode I
2
C-bus Fast-mode Plus
I
2
C-bus
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency
[3]
0 100 0 400 0 1000 kHz
t
BUF
bus free time between a
STOP and START
condition
4.7 - 1.3 - 0.5 - μs
t
HD;STA
hold time (repeated)
START condition
4.0 - 0.6 - 0.26 - μs
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - μs
t
SU;STO
set-up time for STOP
condition
4.0 - 0.6 - 0.26 - μs
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge
time
[1]
0.1 3.45 0.1 0.9 0.05 0.45 μs
t
VD;DAT
data valid time
[2]
300 - 75 - 75 450 ns
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the SCL
clock
4.7 - 1.3 - 0.5 - μs
t
HIGH
HIGH period of the SCL
clock
4.0 - 0.6 - 0.26 - μs
t
f
fall time of both SDA and
SCL signals
[4][6]
- 300 20 + 0.1C
b
[5]
300 - 120 ns
t
r
rise time of both SDA and
SCL signals
[4][6]
- 1000 20 + 0.1C
b
[5]
300 - 120 ns
t
SP
pulse width of spikes that
must be suppressed by the
input filter
[7]
-50 - 50-50ns
Port timing
t
en
enable time output - 80 - 80 - 80 ns
t
dis
disable time output - 40 - 40 - 40 ns
t
v(Q)
data output valid time - 250 - 250 - 250 ns
t
su(D)
data input set-up time 100 - 100 - 100 - ns
t
h(D)
data input hold time 250 - 250 - 250 - ns
Interrupt timing
t
v(INT_N)
valid time on pin INT -4 - 4-4μs
t
rst(INT_N)
reset time on pin INT -4 - 4-4μs
Reset
t
w(rst)
reset pulse width 4 - 4 - 4 - ns
t
rec(rst)
reset recovery time 0 - 0 - 0 - ns
t
rst
reset time 100 - 100 - 100 - ns
