CS5521/22/23/24/28
DS317F8 37
1.4.1.5 Repeated Multiple-Setup Conversions
without Wait
(LP = 1 MC = 1 RC = 0)
In this conversion mode, the ADC will repeatedly
perform conversions, referencing multiple Setups.
The CSRP bits in the command word are ignored in
this mode. Instead, the Depth Pointer (DP3-DP0)
bits in the Configuration Register are accessed to
determine the number of Setups to reference when
collecting the data. The number of Setups refer-
enced will be equal to (DP3-DP0) + 1, and will be
accessed in order, beginning with Setup1. Note that
in this mode, the part will continually perform con-
versions, looping back to Setup1 when finished
with each set, and the user need not read every con-
version set as it becomes available. The SDO line
rises and falls to indicate the availability of new
conversion data sets. When new data is available,
the current conversion data set will be lost, or in the
case that the user has only read a part of the conver-
sion set, the remainder of the conversion set will be
corrupted.
To perform repeated, multiple-Setup conversions
with no wait, the MC bit must be set to '1', the LP
bit must be set to '1', and the RC bit must be set to
'0' in the Configuration Register. Then, the 8-bit
command word to start a conversion must be sent
to the converter. Because the CSRP bits of the
command word are ignored in this mode, a "start
convert" command referencing any of the available
Setups will begin the conversions. The ADC will
then perform conversions using the appropriate
number of Setups (as dictated by the DP bits in the
Configuration Register), beginning with Setup1.
The SDO line will fall after the final conversion to
indicate that the data is ready. Eight SCLKs, plus
24 SCLKs for each Setup referenced are required to
read the conversion words from the data FIFO. The
first 8 SCLKs are used to clear the SDO flag. Ev-
ery 24 bits thereafter consist of the data words of
each Setup that was referenced, until all of the data
has been read from the part. If, during the first 8
SCLKs, "00000000" is provided on SDI, the con-
verter will remain in this conversion mode, and
continue to perform conversions on the desired
number of Setups. To exit this conversion mode,
"1111 1111" must be provided on SDI during the
first 8 SCLKs. If the user decides to exit, 24 more
SCLKs for each referenced Setup are required to
read the final conversion data set from the FIFO
and return to command mode.
1.4.1.6 Repeated Multiple-Setup Conversions
with Wait
(LP = 1 MC = 1 RC = 1)
In this conversion mode, the ADC will repeatedly
perform conversions, referencing multiple Setups.
The CSRP bits in the command word are ignored in
this mode. Instead, the Depth Pointer (DP3-DP0)
bits in the Configuration Register are accessed to
determine the number of Setups to reference when
collecting the data. The number of Setups refer-
enced will be equal to (DP3-DP0) + 1, and will be
accessed in order, beginning with Setup1. Note that
in this mode, every conversion data set must be
read. The part will wait for the current conversion
data set to be read before performing the next set of
conversions.
To perform repeated, multiple-Setup conversions
with wait, the MC bit must be set to '1', the LP bit
must be set to '1', and the RC bit must be set to '1'
in the Configuration Register. Then, the 8-bit com-
mand word to start a conversion must be sent to the
converter. Because the CSRP bits of the command
word are ignored in this mode, a "start convert"
command referencing any of the available Setups
will begin the conversions. The ADC will then per-
form conversions using the appropriate number of
Setups (as dictated by the DP bits in the Configura-
tion Register), beginning with Setup1. The SDO
line will fall after the final conversion to indicate
that the data is ready. Eight SCLKs, plus 24
CS5521/22/23/24/28
38 DS317F8
SCLKs for each Setup referenced are required to
read the conversion words from the data FIFO. The
first 8 SCLKs are used to clear the SDO flag. Ev-
ery 24 bits thereafter consist of the data words of
each Setup that was referenced, until all of the data
has been read from the part. If, during the first 8
SCLKs, "0000 0000" is provided on SDI, the con-
verter will remain in this conversion mode, and be-
gin performing the next set of conversions. To exit
this conversion mode, "1111 1111" must be pro-
vided on SDI during the first 8 SCLKs. If the user
decides to exit, 24 more SCLKs for each referenced
Setup are required to read the final conversion data
set from the FIFO and return to command mode.
1.4.2 Calibration Protocol
To perform a calibration, the user must send a com-
mand byte with its MSB=1, its pointer bits
(CSRP3-CSRP0) set to address the desired Setup to
be calibrated, and the appropriate calibration bits
(CC2-CC0) set to choose the type of calibration to
be performed. Proper calibration assumes that the
CSRs have been previously initialized because the
information concerning the physical channel, its
filter rate, gain range, and polarity, comes from the
channel-setup register being addressed by the
pointer bits in the command byte.
Once the CSRs are initialized, all future calibra-
tions can be performed with one command byte.
Once a calibration cycle is complete, SDO falls and
the results are stored in either the gain or offset reg-
ister for the physical channel being calibrated. Note
that if additional calibrations are performed on the
same physical channel referenced by a different
Setup with different filter rates, gain ranges, or con-
version modes, the last calibration results will re-
place the effects from the previous calibration as
only one offset and gain register is available per
physical channel. One final note is that only one
calibration is performed with each command byte.
To calibrate all the channels additional calibration
commands are necessary.
1.4.3 Example of Using the CSRs to Perform
Conversions and Calibrations
Any time a calibration command is issued (CB=1
and proper CC2-CC0 bits set) or any time a normal
conversion command is issued (CB=1,
CC2=CC1=CC0=0, MC=0), the bits D6-D3 (or
CSRP3 - CSRP0) in the command byte are used as
pointers to address one of the Setups in the chan-
nel-setup registers (CSRs). Five example situations
that a user might encounter when acquiring a con-
version or calibrating the converter follow. These
examples assume that the user is using a CS5528
(16 Setups) and that its CSRs are programmed with
the following physical channel order:
6, 1, 6, 2, 6, 3, 6, 4, 6, 5, 6, 2, 6, 7, 6, 8.
Example 1:
The configuration register has the following bits as
shown: DP3-DP0 = ‘XXXX’, MC = 0, L = 0,
RC = X. The command issued is ‘1111 0000’.
These settings instruct the converter to convert the
15th Setup once, as CPB3 - CPB0 = ‘1110’ (which
happens to be physical channel 6 in this example).
SDO falls after physical channel 6 is converted. To
read the conversion results, 32 SCLKs are then re-
quired. Once acquired, the serial port returns to the
command mode.
Example 2:
The configuration register has the following bits as
shown: DP3-DP0 = ‘XXXX’, MC = 0, LP = 1,
RC = 1. The command byte issued is ‘1001 1000’.
These settings instruct the converter to repeatedly
convert the fourth Setup as CPB3-CPB0 = ‘0011’
(which happens to be physical channel 2 in this ex-
ample). SDO falls after physical channel 2 is con-
verted. To read the conversion results 32 SCLKs
are required. The first 8 SCLKs are needed to clear
the SD0 flag. If ‘0000 0000’ is provided to the SDI
pin during the first 8 SCLKs, the conversion is per-
formed again on physical channel 2. The converter
will remain in data mode until ‘1111 1111’ is pro-
vided during the first 8 SCLKs following the fall of
CS5521/22/23/24/28
DS317F8 39
SD0. After ‘1111 1111’ is provided, 24 additional
SCLKs are required to transfer the last 3 bytes of
conversion data before the serial port will return to
the command mode.
Example 3:
The configuration register has the following bits as
shown: DP3-DP = ‘0101’, MC = 1, LP = 0,
RC = X. The command issued is ‘1XXX X000’.
These settings instruct the converter to perform a
single conversion on six Setups once. The order in
which the channels are converted is 6, 1, 6, 2, 6, and
3. SDO falls after physical channel 3 is converted.
To read the 6 conversion results 8 SCLKs are re-
quired to clear the SD0 flag. Then 144 additional
SCLKs are required to read the conversion data
from the FIFO. Again, the order in which the data
is provided is the same as the order in which the
channels are converted. After the last 3 bytes of the
conversion data corresponding to physical channel
3 is read, the serial port automatically returns to the
command mode where it will remain until the next
valid command byte is received.
Example 4:
The configuration register has the following bits as
shown: DP3-DP0 = ‘1001’, MC = 1, LP = 1,
RC = 0. The command byte issued is
‘1XXX X000’. These settings instruct the convert-
er to repeatedly perform multiple-setup conver-
sions using ten Setups. The order in which the
channels are converted is: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5.
SDO falls after physical channel 5 is converted. To
read the 10 conversion results 8 SCLKs with
SDI = 0 are required to clear the SD0 flag. Then
240 more SCLKs are required to read the conver-
sion data from the FIFO. The order in which the
data is provided is the same as the order in which
the channels are converted. The first 3 bytes of data
correspond to the first Setup which in this example
is physical channel 6; the next 3 bytes of data cor-
respond to the second Setup which in this example
is physical channel 1; and, the last 3 bytes of data
corresponds to 10th Setup which here is physical
channel 5. Since the Setups are converted in the
background, while the data is being read, the user
must finish reading the conversion data FIFO be-
fore it is updated with new conversions. To exit this
conversion mode the user must provide
‘1111 1111’ to SDI during the first 8 SCLKs. If a
byte of 1’s is provided, the serial port returns to the
command mode only after the conversion data
FIFO is emptied (in this case 10 conversions are
performed). Note that in this example physical
channel 6 is converted five times. Each conversion
could be with the same or different filter rates de-
pending on the setting of Setups 1, 3, 5, 7 and 9.
Note that there is only one offset and one gain reg-
ister per physical channel. Therefore, any physical
channel can only be calibrated for the gain range
selected during calibration. Specifying a different
gain range in the Setup other than the range that
was calibrated will result in a gain error.
Example 5:
The configuration register has the following bits as
shown: DP3-DP0 = ‘XXXX’, MC = X, LP = X,
RC = X. The command issued is ‘1010 1101’.
These settings instruct the converter to perform a
system offset calibration of the 6th Setup (which is
physical channel 3 in this example). During cali-
bration, the serial port remains in the command
mode. Once the calibration is completed, SDO
falls. To perform additional calibrations, more
commands have to be issued.
Notes: 1)The configuration register must be written before
channel-setup registers (CSRs) because the depth
information contained in the configuration regis-
ter defines how many of the CSRs to use.
2) The CSRs need to be written regardless of single
conversion or multiple single conversion mode.
3) When single-Setup conversions (MC = 0) are de-
sired, the channel address is embedded in the
command byte. In the multiple-Setup conversion
mode (MC = 1), channels are selected in a pre-
programmed order based on information con-
tained in the CSRs and the depth bits (DP3-DP0)

CS5522-ASZ

Mfr. #:
Manufacturer:
Cirrus Logic
Description:
Analog to Digital Converters - ADC 2-Ch 24-Bit Delta Sigma ADC
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New from this manufacturer.
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