AD7732
Rev. A | Page 12 of 32
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD7732
BIAS0(+)
AIN0(+)
AIN1(+)
BIAS1(+)
RB
RA
SYNC/P1
SCLK
MCLKIN
CS
P0
AV
DD
RESET
BIAS0(–)
AIN0(–)
AIN1(–)
BIAS1(–)
RC
RD
REFIN(+)
DGND
DV
DD
DIN
DOUT
REFIN(–)
AGND
RDY
MCLKOUT
Figure 11. 28-Lead TSSOP
P0
SYNC/P1
AIN0(+)
AIN1(+)
AIN0(–)
BIAS0(+)
BIAS0(–)
AIN1(–)
BIAS1(+)
BIAS1(–)
RA
RB
RC
RD
SCLK
DIN
DOUT
CS
RESET
RDY
DGNDMCLKINMCLKOUTAGND AV
DD
DV
DD
AV
DD
DV
DD
7R
R=15.5k
Ω
2R
R
R
R
7R
7R
7R
2R
2R
2R
BUFFER
REFERENCE
DETECT
REFIN(–) REFIN(+)
AD7732
24-BIT
Σ−Δ
ADC
SERIAL
INTERFACE
CONTROL
LOGIC
CLOCK
GENERATOR
CALIBRATION
CIRCUITRY
I/O PORT
MUX
Figure 12. Block Diagram
Table 10. Pin Function Descriptions—28-Lead TSSOP
Pin No. Mnemonic Description
1
SCLK
Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input
to transfer serial data to or from the AD7732.
2
MCLKIN
Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator
or external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins.
Alternatively, the MCLKIN pin can be driven with a CMOS compatible clock and
MCLKOUT left unconnected.
3
MCLKOUT
When the master clock for the device is a crystal/resonator, the crystal/resonator is
connected between MCLKIN and MCLKOUT. If an external clock is applied to the
MCLKIN, MCLKOUT provides an inverted clock signal or can be switched off to reduce
the device power consumption. MCLK OUT is capable of driving one CMOS load.
4
CS
Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor.
With this input hardwired low, the AD7732 can operate in its 3-wire interface mode
using SCLK, DIN, and DOUT. CS
can be used to select the device in systems with more
than one device on the serial bus. It can also be used as an 8-bit frame
synchronization signal.
5
RESET
Schmitt Triggered Logic Input. Active low input that resets the control logic, interface
logic, digital filter, analog modulator, and all on-chip registers of the part to power-on
status. Effectively, everything on the part except the clock oscillator is reset when the
RESET pin is exercised.
6 AV
DD
Analog Positive Supply Voltage. 5 V to AGND nominal.
7
P0
Digital Input/Output. The pin direction is determined by the P0 DIR bit; the digital
value can be read/written as the P0 bit in the I/O port register. The digital voltage is
referenced to analog supplies. When configured as an input, the pin should be tied
high or low.
AD7732
Rev. A | Page 13 of 32
Pin No. Mnemonic Description
8
SYNC
/P1
SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit;
the digital value can be read/written as the P1 bit in the I/O port register. When the
SYNC bit in the I/O port register is set to 1, the SYNC
/P1 pin can be used to synchronize
the AD7732 modulator and digital filter with other devices in the system. The digital
voltage is referenced to analog supplies. When configured as an input, the pin should be
tied high or low.
9
RA
RA, in association with RB and BIAS0(+), can be used to level shift the positive analog
input 0. In normal circuit configuration, this pin is left open circuit.
10
RB
RB, in association with RA and BIAS0(+), can be used to level shift the positive analog
input 0. In normal circuit configuration, this pin is left open circuit.
11
BIAS1(+)
This input is used to level shift the positive analog input 1. This signal is used to ensure
that the differential signal seen by the internal buffer amplifier is within its common-
mode range. BIAS pins will normally be connected to 2.5 V.
12 AIN1(+) Positive Analog Input Channel 1.
13 AIN0(+) Positive Analog Input Channel 0.
14 BIAS0(+) Voltage Bias for Positive Analog Input 0. This pin has the same function as BIAS1(+).
15 BIAS0(–) Voltage Bias for Negative Analog Input 0. This pin has the same function as BIAS1(+).
16 AIN0(–) Negative Analog Input Channel 0.
17 AIN1(–) Negative Analog Input Channel 1.
18 BIAS1(–) Voltage Bias for Negative Analog Input 1. This pin has the same function as BIAS1(+).
19
RC
RC, in association with RD and BIAS0(–), can be used to level shift the negative analog
input 0. In normal circuit configuration, this pin is left open circuit.
20
RD
RD, in association with RC and BIAS0(–), can be used to level shift the negative analog
input 0. In normal circuit configuration, this pin is left open circuit.
21
REFIN(+)
Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie
anywhere between AV
DD
and AGND. In normal circuit configuration, this pin should be
connected to a 2.5 V reference voltage.
22
REFIN(–)
Negative Terminal of the Differential Reference Input. REFIN(–) voltage potential can lie
anywhere between AV
DD
and AGND. In normal circuit configuration, this pin should be
connected to a 0 V reference voltage.
23 AGND Ground Reference Point for Analog Circuitry.
24
RDY
Logic Output. Used as a status output in both conversion mode and calibration mode. In
conversion mode, a falling edge on this output indicates that either any channel or all
channels have unread data available, according to the RDYFN bit in the I/O port register.
In calibration mode, a falling edge on this output indicates that calibration is complete
(see the Digital Interface Description section for more details).
25
DOUT
Serial data output with serial data being read from the output shift register on the part.
This output shift register can contain information from any AD7732 register, depending
on the address bits of the communications register.
26
DIN
Serial data input (Schmitt triggered) with serial data being written to the input shift
register on the part. Data from this input shift register is transferred to any AD7732
register, depending on the address bits of the communications register.
27 DV
DD
Digital Supply Voltage, 3 V or 5 V Nominal.
28 DGND Ground Reference Point for Digital Circuitry.
AD7732
Rev. A | Page 14 of 32
REGISTER DESCRIPTION
Table 11. Register Summary
Register Addr Dir Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(hex) Default Value
Communications 00 W 0
R/W
6-Bit Register Address
I/O Port 01 R/W P0 P1 P0 DIR P1 DIR RDYFN 0 0 SYNC
P0 Pin P1 Pin 1 1 0 0 0 0
Revision 02 R Chip Revision Code Chip Generic Code
x x x x 0 1 0 0
Test 03 R/W 24-Bit Manufacturing Test Register
ADC Status 04 R – – – – – RDY1 RDY0
0 0 0 0 0 0 0 0
Checksum 05 R/W 16-Bit Checksum Register
ADC Zero-Scale Calibration 06 R/W 24-Bit ADC Zero-Scale Calibration Register
800000h
ADC Full-Scale 07 R/W 24-Bit ADC Full-Scale Register
800000h
Channel Data
1
08, 0A R 16-/24-Bit Data Registers
8000h
Channel Zero-Scale Cal.
1
10, 12 R/W 24-Bit Channel Zero-Scale Calibration Registers
800000h
Channel Full-Scale Cal.
1
18, 1A R/W 24-Bit Channel Full-Scale Calibration Registers
200000h
Channel Status
1
20, 22 R 0 CH1 0 0/P0 RDY/P1 NOREF SIGN OVR
Channel Number 0 0 0 0 0
Channel Setup
1
28, 2A R/W 0 0 0 Stat OPT ENABLE 0 RNG1 RNG0
0 0 0 0 0 0 0 0
Channel Conversion Time
1
30, 32 R/W CHOP FW (7-Bit Filter Word)
1 11h
Mode
2
38, 3A R/W MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP
0 0 0 0 0 0 0 0
1
Bit 1 in the communication register specifies the channel number of the register being accessed.
2
There is only one mode register, although the mode register can be accessed in one of two address locations. The address used to write the mode register specifies the
ADC channel on which the mode will be applied. Only address 38h must be used for reading from the mode register.
Table 12. Operational Mode Summary
MD2 MD1 MD0
Table 13. Input Range Summary
RNG1 RNG0 Mode Nominal Input Voltage Range
0 0 0 Idle Mode 0 0 ±10 V
0 0 1 Continuous Conversion Mode 0 1 0 V to +10 V
0 1 0
Single Conversion Mode 1 0 ±5 V
0 1 1 Power-Down (Standby) Mode
1 1 0 V to +5 V
1 0 0 ADC Zero-Scale Self-Calibration
1 0 1 For Future Use
1 1 0
Channel Zero-Scale System Calibration
1 1 1 Channel Full-Scale System Calibration

AD7732BRUZ-REEL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit
Lifecycle:
New from this manufacturer.
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