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AD7732BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD7732
Rev. A | Page 27 of 32
Analog Input’s Extended Voltage Range
The AD7732 output data code span corresponds to the nominal
input voltage range. The ADC is functional outside the nominal
input voltage range, but the performance might degrade. The
sigma-delta modulator was designed to fully cover a ±11.6 V
differential input voltage; outside this range, the performance
might degrade more rapidly. The adjacent channels are not
affected by up to ±16.5 V absolute analog input voltage
(Figure 8).
When the CLAMP bit in the mode register is set to 1, the
channel data register will be digitally clamped to either all 0s or
all 1s when the analog input voltage goes outside the nominal
input voltage range.
As shown in Table 16 and Table 17 , when CLAMP = 0, the data
reflects the analog input voltage outside the nominal voltage
range. In this case, the SIGN and OVR bits in the channel status
register should be considered along with the data register value
to decode the actual conversion result.
Note that the OVR bit in the channel status register is generated
digitally from the conversion result and indicates the sigma-
delta modulator (nominal) overrange. The OVR bit DOES NOT
indicate exceeding the AIN pin’s absolute voltage limits.
Table 16. Extended Input Voltage Range,
Nominal Voltage Range ±10 V, 16 Bits, CLAMP = 0
Input (V) Data (hex) SIGN OVR
11.60039 147B 0 1
10.00061 0001 0 1
10.00031 0000 0 1
10.00000 FFFF 0 0
0.00031 8001 0 0
0.00000 8000 0 0
–0.00031 7FFF 1 0
–10.00000 0000 1 0
–10.00031 FFFF 1 1
–10.00061 FFFE 1 1
–11.60040 EB85 1 1
Table 17. Extended Input Voltage Range, Nominal
Voltage Range 0 V to +10 V, 16 Bits, CLAMP = 0
Input (V) Data (hex) SIGN OVR
11.60006 28F5 0 1
10.00031 0001 0 1
10.00015 0000 0
1
10.00000 FFFF 0 0
0.00015 0001 0 0
0.00000 0000 0 0
–0.00015 0000 1 1
Chopping
With chopping enabled, the multiplexer repeatedly reverses the
ADC inputs. Every output data result is then calculated as an
average of two conversions, the first with the positive and the
second with the negative offset term included. This effectively
removes any offset error of the input buffer and sigma-delta
modulator.
However, chopping is applied only behind the input resistor
divider stage; therefore, chopping does not eliminate the offset
error and drifts caused by the resistors. Figure 24 shows the
channel signal chain with chopping enabled.
+
-
DIGITAL
INTERFACE
CHOPCHOP
f
MCLK
/2
f
MCLK
/2
BUFFERMULTIPLEXER
DIGITAL
FILTER
SCALING
ARITHMETIC
(CALIBRATIONS)
OUTPUT DATA
AT THE SELECTED
DATA RATE
AIN(+)
AIN(–)
BIAS(+)
BIAS(–)
Σ−Δ
MODULATOR
Figure 24. Channel Signal Chain Diagram with Chopping Enabled
AD7732
Rev. A | Page 28 of 32
Multiplexer, Conversion, and
Data Output Timing
The specified conversion time includes one or two settling and
sampling periods and a scaling time.
With chopping enabled (Figure 25), a conversion cycle starts
with a settling time of 43 MCLK cycles or 44 MCLK cycles (~7
μs with a 6.144 MHz MCLK) to allow the circuits following the
multiplexer to settle. The sigma-delta modulator then samples
the analog signals and the digital filter processes the digital data
stream. The sampling time depends on FW, i.e., on the channel
conversion time register contents. After another settling of 42
MCLK cycles (~6.8 μs), the sampling time is repeated with a
reversed (chopped) analog input signal. Then, during the
scaling time of 163 MCLK cycles (~26.5 μs), the two results
from the digital filter are averaged, scaled using the calibration
registers, and written into the channel data register.
With chopping disabled (Figure 26), there is only one sampling
time preceded by a settling time of 43 MCLK cycles or
44 MCLK cycles and followed by a scaling time of
163 MCLK cycles.
The
RDY
pin goes high during the scaling time, regardless of its
previous state. The relevant RDY bit is set in the ADC status
register and in the channel status register, and the
RDY
pin goes
low when the channel data register is updated and the channel
conversion cycle is finished. If in continuous conversion mode,
the part will automatically continue with a conversion cycle on
the next enabled channel.
Note that every channel can be configured independently for
conversion time and chopping mode. The overall cycle and
effective per channel data rates depend on all enabled
channel settings.
Sigma-Delta ADC
The AD7732 core consists of a charge balancing sigma-delta
modulator and a digital filter. The architecture is optimized for
fast, fully settled conversion. This allows for fast channel-to-
channel switching while maintaining inherently excellent
linearity, high resolution, and low noise.
– CHANNEL 1
SCALING
TIME
SAMPLING
TIME
+ CHANNEL 1
SAMPLING
TIME
SETTLING
TIME
MULTIPLEXER
– CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
Figure 25. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Enabled
SCALING
TIME
CHANNEL 1
SAMPLING
TIME
MULTIPLEXER
CHANNEL 0
RDY
SETTLING
TIME
CONVERSION TIME
Figure 26. Multiplexer and Conversion Timing—Continuous Conversion on Several Channels with Chopping Disabled
AD7732
Rev. A | Page 29 of 32
Frequency Response
The sigma-delta modulator runs at ½ the MCLK frequency,
which is effectively the sampling frequency. Therefore, the
Nyquist frequency is ¼ the MCLK frequency. The digital filter,
in association with the modulator, features the frequency
response of a first order low-pass filter. The –3 dB point is close
to the frequency of 1/channel conversion time. The roll-off is
−20 dB/dec up to the Nyquist frequency. If chopping is enabled,
the input signal is resampled by chopping. Therefore, the overall
frequency response features notches close to the frequency of
1/channel conversion time. The top envelope is again the ADC
response of –20 dB/dec.
The typical frequency response plots are given in Figure 27
and Figure 28. The plots are normalized to 1/channel
conversion time.
NORMALIZED INPUT FREQUENCY
(INPUT FREQUENCY CONVERSION TIME)
GAIN – dB
–60
–50
–40
–30
–20
–10
0
0.1 1.0 10.0
CHOP = 1
Figure 27. Typical ADC Frequency Response, Chopping Enabled
NORMALIZED INPUT FREQUENCY
(INPUT FREQUENCY CONVERSION TIME)
GAIN – dB
–60
–50
–40
–30
–20
–10
0
1.00.1 10.0 100.0 1000.0
CHOP = 0
Figure 28. Typical ADC Frequency Response, Chopping Disabled
Voltage Reference Inputs
The AD7732 has a differential reference input, REF IN(+) and
REF IN(–). The common-mode range for these inputs is from
AGND to AV
DD
. The nominal differential reference voltage for
specified operation is 2.5 V. Both reference inputs feature
dynamic load. Therefore, the reference inputs should be
connected to a low impedance reference voltage source.
External resistance/capacitance combinations may result in gain
errors on the part.
The output noise performance outlined in Table 4 through
Table 9 is for an analog input of 0 V and is unaffected by noise
on the reference. To obtain the same noise performance as
shown in the noise tables over the full input range requires a
low noise reference source for the AD7732. If the reference
noise in the bandwidth of interest is excessive, it will degrade
the performance of the AD7732.
Recommended reference voltage sources for the AD7732
include the AD780, ADR421, REF43, and REF192. Note that in
a typical connection, the voltage reference must be capable of
sinking current flowing out of the BIAS pins through the
internal resistors if a positive voltage is applied to the analog
input. The AD780 meets this requirement. If the voltage
reference used in an application is not capable of sinking
current, an external resistor (5 kΩ) should be connected in
parallel to the REFIN pins.
Reference Detect
The AD7732 includes on-chip circuitry to detect if the part has
a valid reference for conversions. If the voltage between the
REFIN(+) and REFIN(–) pins goes below the NOREF trigger
voltage (0.5 V typ) and the AD7732 is performing a conversion,
the NOREF bit in the channel status register is set.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD7732BRUZ-REEL7

Mfr. #:
Buy AD7732BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit
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New from this manufacturer.
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