AD7732BRUZ-REEL7 Datasheet AD7732BRUZ, AD7732BRUZ-REEL, AD7732BRUZ-REEL7 | P25-P27

AD7732

Rev. A | Page 24 of 32

Dump Mode

When the DUMP bit in the mode register is set to 1, the

channel status register will be read immediately by a read of the

channel data register, regardless of whether the status or the

data register has been addressed through the communications

data in dump mode; otherwise, the AD7732 will be reset.

Figure 18 shows the digital interface signals executing a single

conversion on Channel 0, waiting for the

RDY

pin to go low,

and reading the Channel 0 status register and data register in

the dump mode.

Continuous Conversion Mode

When the mode register is being written, the ADC status byte is

cleared and the

RDY

pin goes high, regardless of its previous

state. When the continuous conversion command is written to

the mode register, the ADC starts conversion on the channel

selected by the address of the mode register.

After the conversion is complete, the relevant channel data

RDY bit in the ADC status register is set, and the AD7732

continues converting on the next enabled channel. The part will

cycle through all enabled channels until put into another mode

or reset. The cycle period will be the sum of all enabled

channels’ conversion times, set by the corresponding channel

conversion time registers.

The RDY bit is reset when the relevant channel data register is

being read. The behavior of the

RDY

pin depends on the

RDYFN bit in the I/O port register. When the RDYFN bit is 0,

the

RDY

pin goes low when any channel has unread data. When

the RDYFN bit is set to 1, the

RDY

pin will only go low if all

enabled channels have unread data.

If an ADC conversion result has not been read before a new

ADC conversion is completed, the new result will overwrite the

previous one. The relevant RDY bit goes low and the

RDY

goes high for at least 163 MCLK cycles (~26.5 μs), indicating

when the data register is updated and the previous conversion

data is lost.

If the data register is being read as an ADC conversion

completes, the data register will not be updated with the new

result (to avoid data corruption) and the new conversion

data is lost.

Figure 19 shows the digital interface signal’s sequence for the

continuous conversion mode with Channels 0 and 1 enabled

and the RDYFN bit set to 0. The

RDY

pin goes low and the data

sequence but with the RDYFN bit set to 1. The

Figure 20

RDY

pin goes

low and all data registers are read after all conversions are

completed. shows the Figure 21

RDY

pin when no data are read

from the AD7732.

DIN

SCLK

DOUT

WRITE

COMMUNICATIONS

WRITE

MODE

RDY

CONVERSION TIME READ DATA

READ

CHANNEL

STATUS

38h 48h 48h

WRITE

COMMUNICATIONS

(00h) (00h) (00h)

STATUS DATA DATA

Figure 18. Serial Interface Signals—Single Conversion Command, 16-Bits Data Reading, Dump Mode

SERIAL

INTERFACE

START

CONTINUOUS

CONVERSION

RDY

CH0 CONVERSION

READ

DATA

CH1

CH1 CONVERSION

CH0 CONVERSION

READ

DATA

CH0

CH1 CONVERSION

READ

DATA

CH0

CH0 CONVERSION

READ

DATA

CH1

Figure 19. Continuous Conversion, CH0 and CH1, RDYFN = 0

AD7732

Rev. A | Page 25 of 32

SERIAL

INTERFACE

START

CONTINUOUS

CONVERSION

RDY

CH0 CONVERSION

READ

DATA

CH1

CH1 CONVERSIONCH0 CONVERSION

READ

DATA

CH0

CH1 CONVERSION

READ

DATA

CH0

CH0 CONVERSION

READ

DATA

CH1

Figure 20. Continuous Conversion, CH0 and CH1, RDYFN = 1

SERIAL

INTERFACE

START

CONTINUOUS

CONVERSION

RDY

CH0 CONVERSIONCH1 CONVERSIONCH0 CONVERSION CH1 CONVERSION CH0 CONVERSION

Figure 21. Continuous Conversion, CH0 and CH1, No Data Read

DIN 24h

00h

DATA

00h

DATA

00h

STATUS

READ

CH0

DATA

READ

CH0

STATUS

48h

WRITE

COMM.

SCLK

DOUT

WRITE

COMM.

WRITE

MODE

RDY

38h 00h

DATA

00h

DATA

00h

STATUS

READ

CH1

DATA

READ

CH1

STATUS

CONVERSION

ON CH0

COMPLETE

CONVERSION

ON CH1

COMPLETE

Figure 22. Continuous Conversion, CH0 and CH1, Continuous Read

Continuous Read (Continuous Conversion) Mode

When the Cont RD bit in the mode register is set, the first write

of 48h to the communications register starts the continuous

read mode. As shown in Figure 22, subsequent accesses to the

part sequentially read the channel status and data registers of

the last completed conversion without any further configuration

of the communications register being required.

Note that the continuous conversion bit in the mode register

should be set when entering the continuous read mode.

Note that the continuous read mode is a dump mode reading of

the channel status and data registers regardless of the dump bit

value. Use the channel bits in the channel status register to

check/recognize that channel data is actually being shifted out.

Note that the last completed conversion result is being read.

Therefore the RDYFN bit in the I/O port register should be 0

and reading the result should always start before the next

conversion is completed.

The AD7732 will stay in continuous read mode as long as the

DIN pin is low while the

pin is low; therefore, write 0 to the

AD7732 while reading in continuous read mode. To exit

continuous read mode, take the DIN pin high for at least 100 ns

after a read is complete. (Write 80h to the AD7732 to exit

continuous reading.)

Taking the DIN pin high does not change the Cont RD bit in

the mode register. Therefore, the next write of 48h starts the

continuous read mode again. To completely stop the continuous

read mode, write to the mode register to clear the Cont RD bit.

AD7732

Rev. A | Page 26 of 32

CIRCUIT DESCRIPTION

The AD7732 is a sigma-delta ADC that is intended for the

measurement of wide dynamic range, low frequency signals in

industrial process control, instrumentation, and PLC systems.

It contains thin film resistor dividers, a multiplexer, an input

buffer, a sigma-delta (or charge balancing) ADC, a digital filter,

a clock oscillator, a digital I/O port, and a serial

communications interface.

Analog Front End

The AD7732 features two fully differential analog inputs. The

on-chip thin film resistor dividers allow ±10 V, ±5 V, 0 V to +10

V, and 0 V to +5 V input signals to be connected directly to the

analog input pins.

The resistor divider input stage is followed by the multiplexer

and then by a wide bandwidth, fast settling time differential

input buffer capable of driving the dynamic load of a high speed

sigma-delta modulator.

In normal circuit configuration, the BIAS pins are connected to

the 2.5 V (reference) voltage source. This ensures that the

differential signal seen by the internal input buffer is within its

absolute/common-mode range of AGND + 200 mV to

– 300 mV.

The AD7732 AIN differential voltage should be within the

specified nominal (up to ±10 V) input range, otherwise the

performance on channel might degrade (see the Analog Input’s

Extended Voltage Range

section).

The AD7732 INL performance varies with the AIN common-

mode voltage (Figure 9). The differential analog input voltage of

±10 V with a common-mode voltage of 0 V means that the AIN

differential voltage is centered around AGND and both AIN(+)

and AIN(–) change within ±5 V respect to AGND. The AD7732

INL also varies with the MCLK frequency (Figure 7).

If the BIAS pins are in normal configuration, the AIN pin

absolute voltage up to ±16.5 V does not degrade the adjacent

channel’s performance. An AIN absolute voltage over ±16.5 V

results in current flowing through the internal protection

diodes located behind the thin film resistors; the adjacent

channel can be affected. By configuring the BIAS and RA to RD

pins differently, the part will work with higher AIN absolute

voltages as long as the internal voltage seen by the multiplexer

and input buffer is within 200 mV to AV

– 300 mV. Absolute

voltage for the AIN, BIAS, and RA to RD pins must never

exceed the values specified in the Absolute Maximum Ratings.

Note that the OVR bit in the channel status register is generated

digitally from the conversion result and indicates the sigma-

delta modulator (nominal) overrange. The OVR bit DOES NOT

indicate exceeding the AIN pin absolute/common-mode

voltage limits.

Figure 23 shows the AD7732 analog input internal structure.

BIAS

AIN

108.5kΩ

15.5kΩ

MUX

PROTECTION

DIODES

AGND

2.1875V ± 1.25V

2.5V

±10V

BUFFER

Figure 23. Simplified Analog Input Internal Structure

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

AD7732BRUZ-REEL7

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit

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AD7732BRUZ-REEL7

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