OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD7732BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
AD7732
Rev. A | Page 18 of 32
Channel Zero-Scale Calibration Registers
24 Bits, Read/Write Registers, Address 10h, 12h, Default Value
800000h
These registers hold the particular channel zero-scale
calibration coefficients. The value in these registers is used in
conjunction with the value in the corresponding channel full-
scale calibration register, the ADC zero-scale calibration
register, and the ADC full-scale register to digitally scale the
particular channel conversion results. The value in this register
is updated automatically following the execution of a channel
zero-scale system calibration.
The format of the channel zero-scale calibration register is a
sign bit and 22 bits unsigned value. Writing this register is
possible in the idle mode only (see the Calibration section for
more details).
Channel Full-Scale Calibration Registers
24 Bits, Read/Write Registers, Address 18h, 1Ah, Default Value
200000h
These registers hold the particular channel full-scale calibration
coefficients. The value in these registers is used in conjunction
with the value in the corresponding channel zero-scale
calibration register, the ADC zero-scale calibration register, and
the ADC full-scale register to digitally scale the particular
channel conversion results. The value in this register is updated
automatically following the execution of a channel full-scale
system calibration. Writing this register is possible in the idle
mode only (see the Calibration section for more details).
Channel Status Registers
8 Bits, Read-Only Register, Address 20h, 22h, Default Value 20h × Channel Number
These registers contain individual channel status information and some general AD7732 status information. Reading the status registers
can be associated with reading the data registers in the dump mode. Reading the status registers is always associated with reading the data
registers in the continuous read mode (see the Digital Interface Description section for more details).
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic 0 CH1 0 0/P0 RDY/P1 NOREF SIGN OVR
Default Channel Number 0 0 0 0 0
Bit Mnemonic Description
7–5 CH1
These bits reflect the channel number. This can be used for current channel identification and easier
operation of the dump mode and continuous read mode.
4 0/P0
When the status option bit of the corresponding channel setup register is reset to 0, this bit is read as a zero.
When the status option bit is set to 1, this bit reflects the state of the P0 pin, whether it is configured as an
input or an output.
3 RDY/P1
When the status option bit of the corresponding channel setup register is reset to 0, this bit reflects the
selected channel RDY bit in the ADC status register. When the status option bit is set to 1, this bit reflects the
state of the P1 pin, whether it is configured as an input or an output.
2 NOREF
This bit indicates the reference input status. If the voltage between the REFIN(+) and REFIN(–) pins is less than
NOREF, the trigger voltage and a conversion is executed, then the NOREF bit goes to 1.
1 SIGN The voltage polarity at the analog input. It will be 0 for a positive voltage and 1 for a negative voltage.
0 OVR
This bit reflects either the overrange or the underrange on the analog input. The bit is set to 1 when the
analog input voltage goes over or under the nominal voltage range (see the Analog Input’s Extended Voltage
Range section).
AD7732
Rev. A | Page 19 of 32
Channel Setup Registers
8 Bits, Read/Write Register, Address 28h, 2Ah, Default Value 00h
These registers are used to configure the selected channel, to configure its input voltage range, and to set up the corresponding channel
status register.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic 0 0 0 Stat OPT ENABLE 0 RNG1 RNG0
Default 0 0 0 0 0 0 0 0
Bit Mnemonic Description
7–5 0 These bits must be 0 for proper operation.
4 Stat OPT
Status Option. When this bit is set to 1, the P0 and P1 bits in the channel status register will reflect the state of
the P0 and P1 pins. When this bit is reset to 0, the RDY bit in the channel status register will reflect the channel
corresponding to the RDY bit in the ADC status register.
3 ENABLE
Channel Enable. Set this bit to 1 to enable the channel in the continuous conversion mode. A single
conversion will take place regardless of this bit’s value.
2 0 This bit must be 0 for proper operation.
1–0 RNG1–RNG0 This is the channel input voltage range (see Table 15).
Table 15.
RNG1 RNG0 Nominal Input Voltage Range
0 0 ±10 V
0 1 0 V to +10 V
1 0 ±5 V
1 1 0 V to +5 V
Channel Conversion Time Registers
8 Bits, Read/Write Register, Address 30h, 32h, Default Value 91h
The conversion time registers enable or disable chopping and configure the digital filter for a particular channel. This register value
affects the conversion time, frequency response, and noise performance of the ADC.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic CHOP FW (7-Bit Filter Word)
Default 1 11h
Bit Mnemonic Description
7 CHOP Chopping Enable Bit. Set to 1 to apply chopping mode for a particular channel.
6–0 FW
CHOP = 1, single conversion or continuous conversion with one channel enabled.
Conversion Time (μs) = (FW × 128 + 248)/MCLK Frequency (MHz), the FW range is 2 to 127.
CHOP = 1, continuous conversion with two channels enabled.
Conversion Time (μs) = (FW × 128 + 249)/MCLK Frequency (MHz), the FW range is 2 to 127.
CHOP = 0, single conversion or continuous conversion with one channel enabled.
Conversion Time (μs) = (FW × 64 + 206)/MCLK Frequency (MHz), the FW range is 3 to 127.
CHOP = 0, continuous conversion with two channels enabled.
Conversion Time (μs) = (FW × 64 + 207)/MCLK Frequency (MHz), the FW range is 3 to 127.
AD7732
Rev. A | Page 20 of 32
Mode Register
8 Bits, Read/Write Register, Address 38h, 3Ah, Default Value 00h
The mode register configures the part and determines its operating mode. Writing to the mode register clears the ADC status register, sets
the
RDY
pin to a logic high level, exits all current operations, and starts the mode specified by the mode bits.
The AD7732 contains only one mode register. Bit 1 of the address is used for writing to the mode register to specify the channel selected
for the operation determined by the MD2 to MD0 bits. Only the address 38h must be used for reading from the mode register.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mnemonic MD2 MD1 MD0 CLKDIS DUMP Cont RD 24/16 BIT CLAMP
Default 0 0 0 0 0 0 0 0
Bit Mnemonic Description
7–5 MD2–MD0
Mode Bits. These three bits determine the AD7732 operation mode. Writing a new value to the mode bits will
exit the part from the mode in which it has been operating and place it in the newly requested mode
immediately. The function of the mode bits is described in more detail below.
4 CLKDIS
Master Clock Output Disable. When this bit is set to 1, the master clock is disabled from appearing at the
MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the MCLKOUT as a
power saving feature. When using an external clock on MCLKIN, the AD7732 continues to have internal clocks
and will convert normally regardless of the CLKDIS bit state. When using a crystal oscillator or ceramic
resonator across the MCLKIN and MCLKOUT pins, the AD7732 clock is stopped and no conversions can take
place when the CLKDIS bit is active. The AD7732 digital interface can still be accessed using the SCLK pin.
3 DUMP
DUMP Mode. When this bit is reset to 0, the channel status register and channel data register will be
addressed and read separately. When the DUMP bit is set to 1, the channel status register will be followed
immediately by a read of the channel data register regardless of whether the status or data register has been
addressed through the communication register. The continuous read mode will always be dump mode
reading of the channel status and data register, regardless of the dump bit value (see the Digital Interface
Description section for more details).
2 Cont RD
When this bit is set to 1, the AD7732 will operate in the continuous read mode (see the Digital Interface
Description section for more details).
1 24/16 BIT
The Channel Data Register Data Width Selection Bit. When set to 1, the channel data registers will be 24 bits
wide. When set to 0, the channel data registers will be 16 bits wide.
0 CLAMP
This bit determines the channel data register’s value when the analog input voltage is outside the nominal
input voltage range. When the CLAMP bit is set to 1, the channel data register will be digitally clamped either
to all 0s or all 1s when the analog input voltage goes outside the nominal input voltage range. When the
CLAMP bit is reset to 0, the data registers reflect the analog input voltage even outside the nominal voltage
range (see the Analog Input’s Extended Voltage Range section).
MD2 MD1 MD0 Mode Address Used for Mode Register Write Specifies:
0 0 0 Idle Mode
0 0 1 Continuous Conversion Mode The First Channel to Start Converting
0 1 0 Single Conversion Mode Channel to Convert
0 1 1 Power-Down (Standby) Mode
1 0 0 ADC Zero-Scale Self-Calibration Channel Conversion Time Used for the ADC Self-Calibration
1 0 1 For Future Use
1 1 0 Channel Zero-Scale System Calibration Channel to Calibrate
1 1 1 Channel Full-Scale System Calibration Channel to Calibrate
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD7732BRUZ-REEL7

Mfr. #:
Buy AD7732BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet