AD7732BRUZ-REEL7 Datasheet AD7732BRUZ, AD7732BRUZ-REEL, AD7732BRUZ-REEL7 | P16-P18

AD7732

Rev. A | Page 15 of 32

The AD7732 is configurable through a series of registers. Some

of them configure and control general AD7732 features, while

others are specific to each channel. The register data widths

vary from 8 bits to 24 bits. All registers are accessed through the

communications register, i.e., any communication to the

AD7732 must start with a write to the communications register

specifying which register will be subsequently read or written.

Communications Register

8 Bits, Write-Only Register, Address 00h

All communications to the part must start with a write

operation to the communications register. The data written to

the communications register determines whether the

subsequent operation will be a read or write and to which

defaults to expect write operation to the communications

or write operation to the selected register is complete. If the

interface sequence is lost, the part can be reset by writing at

least 32 serial clock cycles with DIN high and

low. (Note that

all of the parts, including the modulator, filter, interface, and all

registers are reset in this case.) Remember to keep DIN low

while reading 32 bits or more either in continuous read mode or

with the DUMP bit and “24/16” bit in the mode register set.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic 0

R/W

6-Bit Register Address

Bit Mnemonic Description

7 0 This bit must be 0 for proper operation.

R/W

A 0 in this bit indicates that the next operation will be a write to a specified register. A 1 in this bit indicates

that the next operation will be a read from a specified register.

5–0

Address

Address specifying to which register the read or write operation will be directed. For channel specific registers,

Bit 1 specifies the channel number. When the subsequent operation writes to the Mode register, Bit 1 specifies

the channel selected for operation determined by the mode register value (see Table 14).

Table 14.

Bit 2 Bit 1 Bit 0 Channel Input

0 0 0 0 AIN0(+) – AIN0(–)

0 1 0 1 AIN1(+) – AIN1(–)

AD7732

Rev. A | Page 16 of 32

I/O Port Register

8 Bits, Read/Write Register, Address 01h, Default Value 30h + Digital Input Value × 40h

The bits in this register are used to configure and access the digital I/O port on the AD7732.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic P0 P1 P0 DIR P1 DIR RDYFN 0 0 SYNC

Default P0 Pin P1 Pin 1 1 0 0 0 0

Bit Mnemonic Description

7, 6 P0, P1

When the P0 and P1 pins are configured as outputs, the P0 and P1 bits determine the pins’ output level. When

the P0 and P1 pins are configured as inputs, the P0 and P1 bits reflect the current input level on the pins.

5, 4 P0 DIR, P1 DIR

These bits determine whether the P0 and P1 pins are configured as inputs or outputs. When set to 1, the

corresponding pin will be an input; when reset to 0, the corresponding pin will be an output.

3 RDYFN

This bit is used to control the function of the RDY

pin on the AD7732. When this bit is reset to 0, the RDY pin

goes low when any channel has unread data. When this bit is set to 1, the RDY

pin will only go low if all

enabled channels have unread data.

2, 1 0 These bits must be 0 for proper operation.

0 SYNC

This bit enables the SYNC

pin function. By default, this bit is 0 and SYNC/P1 can be used as a digital I/O pin.

When the SYNC bit is set to 1, the SYNC

pin can be used to synchronize the AD7732 modulator and digital

filter with other devices in the system.

Revision Register

8 Bits, Read-Only Register, Address 02h, Default Value 04h + Chip Revision × 10h

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic Chip Revision Code Chip Generic Code

Default x x x x 0 1 0 0

Bit Mnemonic Description

7–4 Chip Revision Code 4-Bit Factory Chip Revision Code

3–0 Chip Generic Code On the AD7732, these bits will read back as 04h.

Test Register

24 Bits, Read/Write Register, Address 03h

This register is used for testing the part in the manufacturing process. The user must not change the default configuration of this register.

AD7732

Rev. A | Page 17 of 32

ADC Status Register

8 Bits, Read-Only Register, Address 04h, Default Value 00h

In conversion modes, the register bits reflect the individual channel status. When a conversion is complete, the corresponding channel

data register is updated and the corresponding RDY bit is set to 1. When the channel data register is read, the corresponding bit is reset to

0. The bit is also reset to 0 when no read operation has taken place and the result of the next conversion is being updated to the channel

data register. Writing to the mode register resets all the bits to 0.

In calibration modes, all the register bits are reset to 0 while a calibration is in progress; all the register bits are set to 1 when the

calibration is complete.

The

RDY

pin output is related to the content of the ADC status register as defined by the RDYFN bit in the I/O port register.

The RDY0 bit corresponds to the differential input 0, and the RDY1 bit corresponds to the differential input 1.

Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Mnemonic – – – – – RDY1 – RDY0

Default 0 0 0 0 0 0 0 0

Checksum Register

16 Bits, Read/Write Register, Address 05h

This register is described in the Using the

AD7732/AD7734/AD7738/AD7739 Checksum Register

application note, (www.analog.com/AN-626).

ADC Zero-Scale Calibration Register

24 Bits, Read/Write Register, Address 06h, Default Value 800000h

The register holds the ADC zero-scale calibration coefficient.

The value in this register is used in conjunction with the value

in the ADC full-scale calibration register and the corresponding

channel zero-scale and channel full-scale calibration registers to

scale digitally all channels’ conversion results. The value in this

ADC zero-scale self-calibration. Writing this register is

possible in the idle mode only (see the Calibration section for

more details).

ADC Full-Scale Register

24 Bits, Read/Write Register, Address 07h, Default Value 800000h

This register holds the ADC full-scale coefficient. The user is

advised not to change the default configuration of this register.

Channel Data Registers

16 Bit/24 Bit, Read-Only Registers, Address 08h, 0Ah, Default

Width 16 Bits, Default Value 8000h

These registers contain the most up-to-date conversion results

corresponding to each analog input channel. The 16-bit or 24-

bit data width can be configured by setting the 16 bit/24 bit in

the mode register. The relevant RDY bit in the channel status

return low once the data register reading has begun. The

RDY

pin can be configured to indicate when any channel has unread

data or waits until all enabled channels have unread data. If any

channel data register read operation is in progress when a new

result is updated, no update of the data register will occur. This

avoids having corrupted data. Reading the status registers can

be associated with reading the data registers in the dump mode.

Reading the status registers is always associated with reading

the data registers in the continuous read mode (see the Digital

Interface Description section for more details).

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

AD7732BRUZ-REEL7

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Analog Devices Inc.

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Analog to Digital Converters - ADC 2Ch+/-10V InputRange 24-Bit

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AD7732BRUZ-REEL7

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