USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001715A-page 13
1
Reference
Clock Select
1 Input
REFSEL1 IS This signal, combined with REFSEL0, selects the
reference clock input frequency. The reference
select input must be set to correspond to the
frequency applied to the REFCLK input. Refer to
Section 8.4, "Reference Clock," on page 41 for
additional information.
1
System Reset
Input
RESET_N I_RST This active-low signal allows external hardware to
reset the device.
Note: The active-low pulse must be at least
5us wide. Refer to Section 8.3.2,
"External Chip Reset (RESET_N)," on
page 40 for additional information.
1
External USB
Transceiver
Bias Resistor
RBIAS AI A 12.0kΩ (+/- 1%) resistor is attached from
ground to this pin to set the transceiver’s internal
bias settings.
1
Hub Connect
Input
HUB_CONN IS This signal is used to control the hub
communication stage. The device will transition
to the hub communications stage when this pin is
asserted high. Two methods of use may be used:
Tie to +3.3V: The hub will automatically transition
to the communications stage when configuration
is complete.
Transition from low to high: The hub will
transition to the communications stage after
configuration is complete and this signal
transitions from low to high.
Refer to Section 8.5, "Hub Connect
(HUB_CONN)," on page 42 for additional
information.
1
Charge
Detect 0
Output
CHRGDET0 O8 This signal, in conjunction with CHRGDET1, can
be configured to communicate information that
can affect the level of current that the system
may draw from the upstream USB VBUS wire.
Refer to Section 8.1.1.1, "Charger Detection
(CHRGDET[1:0])," on page 37 for additional
information.
1
Charge
Detect 1
Output
CHRGDET1 O8 This signal, in conjunction with CHRGDET0, can
be configured to communicate information that
can affect the level of current that the system
may draw from the upstream USB VBUS wire.
Refer to Section 8.1.1.1, "Charger Detection
(CHRGDET[1:0])," on page 37 for additional
information.
Table 3.1 Ball Descriptions (continued)
NUM
BALLS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
DS00001715A-page 14 2014 Microchip Technology Inc.
1
Suspend
Output
SUSPEND PU This signal is used to indicate that the entire hub
has entered the USB suspend state and that
VBUS current consumption should be reduced in
accordance with the USB specification. Refer to
Section 8.7, "Suspend (SUSPEND)," on page 42
for additional information.
Note: SUSPEND must be enabled via the
Protouch configuration tool.
Interrupt
Request Input
IRQ_N IS This active-low signal allows external hardware to
interrupt the device. Refer to Section 8.8,
"Interrupt Requests (IRQ_N)," on page 43 for
additional information.
Interrupt
Output
INT_N OD8 This active-low signal allows the device to output
an interrupt to external hardware. Refer to
Section 8.9, "Interrupt Output (INT_N)," on
page 43 for additional information.
1
USB Port
Control
PRTCTLA OD8/IS
(PU)
This pin functions as both the downstream USB
port power enable output (PRTPWRA) and the
downstream USB port over-current sense input
(OCSA_N).
POWER
1
Battery
Power Supply
Input
VBAT P Battery power supply input. When VBAT is
connected directly to a +3.3V supply from the
system, the internal +3.3V regulator runs in
dropout and regulator power consumption is
eliminated. A 4.7 μF (<1
Ω ESR) capacitor to
ground is required for regulator stability. The
capacitor should be placed as close as possible
to the device. Refer to Chapter 4, "Power
Connections," on page 17 for power connection
information.
1
+3.3V Power
Supply
VDD33 P +3.3V power supply. A 1.0 μF (<1
Ω ESR)
capacitor to ground is required for regulator
stability. The capacitor should be placed as close
as possible to the device. Refer to Chapter 4,
"Power Connections," on page 17 for power
connection information.
1
+1.8-3.3V
Core Power
Supply Input
VDDCOREREG P +1.8-3.3V core power supply input to internal
+1.2V regulator. This pin may be connected to
VDD33 for single supply applications when VBAT
equals +3.3V. Running in a dual supply
configuration with VDDCOREREG at a lower
voltage, such as +1.8V, may reduce overall
system power consumption. Refer to Chapter 4,
"Power Connections," on page 17 for power
connection information.
1
+1.2V Core
Power Supply
VDDCR12 P +1.2V core power supply. A 1.0 μF (<1
Ω ESR)
capacitor to ground is required for regulator
stability. The capacitor should be placed as close
as possible to the device. Refer to Chapter 4,
"Power Connections," on page 17 for power
connection information.
Table 3.1 Ball Descriptions (continued)
NUM
BALLS NAME SYMBOL
BUFFER
TYPE DESCRIPTION
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001715A-page 15
Note 3.2 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of
RESET_N (external chip reset). Configuration straps are identified by an underlined
symbol name. Signals that function as configuration straps must be augmented with an
external resistor when connected to a load. Refer to Section 6.3, "Device Configuration
Straps," on page 26 for additional information.
3.2 Pin Assignments
2 Ground GND P Ground
Table 3.2 30-WLCSP Package Ball Assignments
BALL123456
A SUSPEND/
IRQ_N/INT_N
DP0 DM0 REFCLK
VDDCOREREG
VDDCR12
B HUB_CONN RESET_N GND VDD33 VBAT STRB1
C REFSEL0 SCL/
SMBCLK
RBIAS GND DATA1 DP2
D SDA/
SMBDATA
SPI_CLK SPI_DO/
SPI_SPD_SEL
CHRGDET0 DM2 DP3
E SPI_CE_N SPI_DI PRTCTLA CHRGDET1 DM3 REFSEL1
Table 3.1 Ball Descriptions (continued)
NUM
BALLS NAME SYMBOL
BUFFER
TYPE DESCRIPTION

USB3813I-1080XY-TR

Mfr. #:
Manufacturer:
Microchip Technology
Description:
USB Interface IC USB 2.0 Hi-Spd 3-pt Hub Cntlr
Lifecycle:
New from this manufacturer.
Delivery:
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