USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001715A-page 29
7.1.2 Operation of the Dual High Speed Read Sequence
The SPI controller also supports dual data mode. When configured in dual mode, the SPI controller
will automatically handle XDATA reads going out to the SPI ROM. When the controller detects a read,
the controller drives SPI_CE_N low and outputs 0x3B (the value must be programmed into the SPI_
FR_OPCODE Register) followed by the 24 bit address. Bits 23 through Bit 17 are forced to zero, and
address bits 16 through 0 are directly from the XDATA address bus. Because it is in fast read mode,
the SPI controller then outputs a DUMMY byte. The next four clocks will clock-in the first byte. The
data appears two bits at a time on SPI_DO and SPI_DI. When the first byte is clocked in, a ready
signal is sent back to the processor, and the processor gets one byte.
After the processor gets the first byte, its address will change. If the address is one more than the last
address, the SPI controller will clock out one more byte. If the address in anything other than one more
than the last address, the SPI controller will terminate the transaction by driving SPI_CE_N high. As
long as the addresses are sequential, the SPI Controller will continue clocking data in.
7.1.3 32 Byte Cache
There is a 32-byte pipeline cache with an associated base address pointer and length pointer. Once
the SPI controller detects a jump, the base address pointer is initialized to that address. As each new
sequential data byte is fetched, the data is written into the cache and the length is incremented. If the
sequential run exceeds 32 bytes, the base address pointer is incremented to indicate the last 32 bytes
fetched. If the firmware performs a jump, and the jump is in the cache address range, the fetch is done
in 1 clock from the internal cache instead of an external access.
7.1.4 Interface Operation to the SPI Port When Not Performing Fast Reads
There is a 8-byte command buffer (SPI_CMD_BUF[7:0]), an 8-byte response buffer
(SPI_RESP_BUF[7:0]), and a length register that counts out the number of bytes (SPI_CMD_LEN).
Additionally, there is a self-clearing GO bit in the SPI_CTL register. Once the GO bit is set, device
drives SPI_CE_N low and starts clocking. It will then output SPI_CMD_LEN x 8 number of clocks. After
the first COMMAND byte has been sent out, the SPI_DI input is stored in the SPI_RESP buffer. If the
SPI_CMD_LEN is longer than the SPI_CMD_BUF, don’t cares are sent out on the SPI_DO output.
This mode is used for program execution out of internal RAM or ROM.
Figure 7.2 SPI Dual Hi-Speed Read Sequence
SPI_CE_N
SPI_CLK
SPI_DO
SPI_DI
8
0B
MSB
HIGH IMPEDANCE
15 16
123
405
7
6
D1
ADD.
23 24
ADD. ADD.
X
39 40
31
32
44
47 48
51 52
55 56
59
D2
NN+1
D3
N+2
D4
N+3
D5
N+4
MSB
MSB
D1 D2
N
N+1
D3
N+2
D4
N+3
D5
N+4
MSB
43
Bits-7,5,3,1 Bits-7,5,3,1 Bits-7,5,3,1 Bits-7,5,3,1
Bits-6,4,2,0
Bits-6,4,2,0 Bits-6,4,2,0
Bits-6,4,2,0
Bits-7,5,3,1
Bits-6,4,2,0
