USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001715A-page 33
7.1.8 JEDEC-ID Read Example
To perform a JEDEC-ID command, the device writes 0x9F into the first byte of the SPI_CMD_BUF.
The length of the transfer is 4 bytes. The device first drives SPI_CE_N low, then SPI_DO is output
with 8 bits of the command, followed by the 24 bits of dummy bytes (due to the length being set to 4).
When the transfer is complete, SPI_CE_N goes high. After the first byte, the data on SPI_DI is clocked
into the SPI_RSP_BUF. At the end of the command, there are three valid bytes in the SPI_RSP_BUF.
In this example, 0xBF, 0x25, 0x8E.
7.2 I
2
C Master Interface
The I
2
C master interface implements a subset of the I
2
C Master Specification (Please refer to the
Philips Semiconductor Standard I
2
C-Bus Specification for details on I
2
C bus protocols). The device’s
I
2
C master interface conforms to the Standard-Mode I
2
C Specification (100 kbit/s transfer rate and 7-
bit addressing) for protocol and electrical compatibility. The device acts as the master and generates
the serial clock SCL, controls the bus access (determines which device acts as the transmitter and
which device acts as the receiver), and generates the START and STOP conditions.
Note: Extensions to the I
2
C Specification are not supported.
Note: All device configuration must be performed via the Pro-Touch Programming Tool. For additional
information on the Pro-Touch programming tool, contact your local sales representative.
7.2.1 I
2
C Message Format
7.2.1.1 Sequential Access Writes
The I
2
C interface supports sequential writing of the device’s register address space. This mode is
useful for configuring contiguous blocks of registers. Figure 7.7 shows the format of the sequential
Figure 7.6 SPI JEDEC-ID Read Sequence
SPI_CE_N
SPI_CLK
SPI_DO
SPI_DI
8
9F
MSB
HIGH IMPEDANCE
1112 13
14 15
16
123
405
7
6
109
17 18
19
20 21 22 23
24
25 26
27
2829
30 31
32 33
34
BF 25
8E
MSB
MSB
