USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
DS00001715A-page 22 2014 Microchip Technology Inc.
signature of “2DFU” (device firmware upgrade) beginning at address 0xFFFA. If a valid signature is
found, then the external ROM is enabled and the code execution begins at address 0x0000 in the
external SPI device. If a valid signature is not found, then execution continues from internal ROM. SPI
ROMs used with the device must be 1 Mbit and support either 30 MHz or 60 MHz. The frequency
used is set using the SPI_SPD_SEL
configuration strap. Both 1- and 2-bit SPI operation is supported.
For optimum throughput, a 2-bit SPI ROM is recommended. Both mode 0 and mode 3 SPI ROMS are
also supported. Refer to Section 6.3.1, "SPI Speed Select (SPI_SPD_SEL)," on page 27 for additional
information on selection of the SPI speed.For all other configurations, the firmware checks for the
presence of an external I
2
C/SMBus. It does this by asserting two pull down resistors on the data and
clock lines of the bus. The pull downs are typically 50Kohm. If there are 10Kohm pull-ups present, the
device becomes aware of the presence of an external SMBus/I
2
C bus. If a bus is detected, the
firmware transitions to the SOC_CFG state.
5.1.6 SOC Configuration Stage (SOC_CFG)
In this stage, the SOC may modify any of the default configuration settings specified in the integrated
ROM such as USB device descriptors, or port electrical settings, and control features such as
upstream battery charging detection.
There is no time limit. In this stage the firmware will wait indefinitely for the SMBus/I
2
C configuration.
When the SOC has completed configuring the device, it must write to register 0xFF to end the
configuration.
5.1.7 Configuration Stage (CONFIG)
Once the SOC has indicated that it is done with configuration, then all the configuration data is
combined. The default data, the SOC configuration data, the OTP data are all combined in the firmware
and device is programmed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or
Hub.Connect present. Once VBUS is present, and upstream battery charging is enabled, the device
will transition to the Battery Charger Detection Stage (CHGDET). If VBUS is present, and upstream
battery charging is not enabled, the device will transitions to the Connect (Hub.Connect) stage.
5.1.8 Battery Charger Detection Stage (CHGDET)
After configuration, if enabled, the device enters the Battery Charger Detection Stage. If the battery
charger detection feature was disabled during the CONFIG stage, or the HUB_CONN pin is asserted,
the device will immediately transition to the Hub Connect (Hub.Connect) stage. If the battery charger
detection feature remains enabled, the battery charger detection sequence is started automatically.
If a charger is detected during this stage, the device asserts the CHRGDET[1:0] output pin function if
the charger type identified is not masked. If the charger detection remains enabled, the device will
transition to the Hub.Connect stage if using the hardware detection mechanism.
5.1.9 Hub Connect Stage (Hub.Connect)
Once the CHGDET stage is completed, the device enters the Hub.Connect stage. USB connect can
be initiated by asserting the HUB_CONN pin high. The device will remain in the Hub.Connect stage
indefinitely until the HUB_CONN pin is deasserted.
5.1.10 Normal Mode
Lastly the SOC enters the Normal Mode of operation. In this stage, full USB operation is supported
under control of the USB Host on the upstream port. The device will remain in the normal mode until
the operating mode is changed by the system.
