USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
DS00001715A-page 52
2014 Microchip Technology Inc.
9.6 Clock Specifications
The device can accept a 24 MHz single-ended clock oscillator input. REFCLK should be driven with a
clock that adheres to the specifications outlined in Section 9.6.1, "External Reference Clock
(REFCLK)".
9.6.1 External Reference Clock (REFCLK)
The following input clock specifications are suggested:
± 350 PPM
The input frequency of REFCLK is user configurable. Refer to Section 8.4, "Reference Clock" for
additional information on configuring a reference clock input.
Note: The external clock is recommended to conform to the signalling levels designated in the
JEDEC specification on 1.2V CMOS Logic.
Table 9.8 SPI Timing Values (60 MHz Operation)
SYMBOL DESCRIPTION MIN TYP MAX UNITS
t
fc
Clock frequency 60 MHz
t
ceh
Chip enable (SPI_CE_EN) high time 50 ns
t
clq
Clock to input data 9 ns
t
dh
Input data hold time 0 ns
t
os
Output setup time 5 ns
t
oh
Output hold time 5 ns
t
ov
Clock to output valid 4 ns
t
cel
Chip enable (SPI_CE_EN) low to first clock 12 ns
t
ceh
Last clock to chip enable (SPI_CE_EN) high 12 ns
