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USB3813I-1080XY-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001715A-page 43
8.8 Interrupt Requests (IRQ_N)
The IRQ_N I
2
C request input pin may be used by the SOC when it desires to communicate with the
device during the HUB.Communication stage, assuring the device’s SMBus is active and ready to
respond - even during USB suspend. In order to meet USB suspend current limits, most blocks in the
device, including the SMBus controller, are in a low power state and are not capable of operation.
When the device observes the assertion of IRQ_N, if the device is in suspend mode, it will enable to
PLL and allow serial communication to be achieved. When the IRQ_N pin is negated the device will
return to its normal suspend current consumption. The IRQ_N alternate function can be implemented
at the same time as the INT_N interrupt output, on the same physical pin.
Note: Asserting the IRQ_N input while the device is in suspend mode will increase the instantaneous
current consumption above the average suspend current requirement. Therefore, this feature
should be used briefly and sparingly.
8.9 Interrupt Output (INT_N)
INT_N is a general interrupt pin intended to communicate select condition changes within the device.
The conditions which may cause an interrupt are detailed in the . The conditions which cause the
interrupt to assert can be controlled through use of the Serial Port Interrupt Mask Register.
The general interrupt and all interrupt conditions are functionally latched and event driven. Once the
interrupt or any of the conditions have asserted, the status bit will remain asserted until the SOC
negates the bit using the SMBus. The bits will then remain negated until a new event condition occurs.
The latching nature of the register causes the status to remain even if the condition that caused the
interrupt ceases to be active. The event driven nature of the register causes the interrupt to only occur
when a new event occurs - when a condition is removed and then is applied again. For example, if
the battery charger detection routine has completed and the SOC negates the interrupt status, it will
not cause an interrupt just because the charger detection is still completed. A new charger detection
routine must run before the associated interrupt will assert again.
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
DS00001715A-page 44
2014 Microchip Technology Inc.
Chapter 9 Operational Characteristics
9.1 Absolute Maximum Ratings*
VBAT Supply Voltage (Note 9.1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +5.5 V
VDDCOREREG Supply Voltage (Note 9.1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +3.6 V
Positive voltage on input signal pins, with respect to ground (Note 9.2) . . . . . . . . . . . . . . . . . . . . 3.6 V
Negative voltage on input signal pins, with respect to ground (Note 9.3). . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on REFCLK, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDDCR12
Positive voltage on HSIC signals, with respect to ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.32 V
Positive voltage on USB DP/DM signals, with respect to ground (Note 9.4) . . . . . . . . . . . . . . . . . 5.5 V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55
o
C to +150
o
C
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..JEDEC Class 3A
Note 9.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested to use a clamp circuit.
Note 9.2 This rating does not apply to the following signals: All USB DM/DP pins, REFCLK, and all
HSIC signals.
Note 9.3 This rating does not apply to the HSIC signals.
Note 9.4 This rating applies only when VDD33 is powered.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 9.2, "Operating Conditions**", Section 9.4, "DC Specifications", or any other applicable section
of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified
otherwise.
USB 2.0 Hi-Speed 3-Port Hub Controller Optimized for Portable Applications
Datasheet
2014 Microchip Technology Inc. DS00001715A-page 45
9.2 Operating Conditions**
VBAT Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+2.9 V to +5.5 V
VDDCOREREG Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.5
Power Supply Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.6
Ambient Operating Temperature in Still Air (T
A
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.7
Note 9.5 +1.6 V to +2.0 V when VDDCOREREG is connected to an external +1.8V power supply,
+3.0 V to +3.6 V when VDDCOREREG is connected to VDD33.
Note 9.6 The power supply rise time requirements vary dependent on the usage of the external
reset (RESET_N). If RESET_N is asserted at power-on, the power supply rise time must
be 10mS or less (t
RT(max)
= 10mS). If RESET_N is not used at power-on (tied high), the
power supply rise time must be 1mS or less (t
RT(max)
= 1mS). Higher voltage supplies must
always be at an equal or higher voltage than lower voltage supplies. Figure 9.1 illustrates
the supply rise time requirements.
Note 9.7 0
o
C to +70
o
C for commercial version, -40
o
C to +85
o
C for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
Figure 9.1 Single/Dual Supply Rise Time Models
t
10%
10%
90%
Voltage
t
RT
t
90%
Time
100%
3.3V/VBAT
VSS
VBAT
t
10%
10%
90%
Voltage
t
RT
t
90%
Time
100%
3.3V
VSS
VBAT
90%
100%
1.8V
VDDCOREREG
Single Supply Rise Time Model Dual Supply Rise Time Model
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

USB3813I-1080XY-TR

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Buy USB3813I-1080XY-TR
Manufacturer:
Microchip Technology
Description:
USB Interface IC USB 2.0 Hi-Spd 3-pt Hub Cntlr
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