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AD9515BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
1.6 GHz Clock Distribution IC, Dividers,
Delay Adjust, Two Outputs
Data Sheet
AD9515
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2012 Analog Devices, Inc. All rights reserved.
FEATURES
1.6 GHz differential clock input
2 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
1.6 GHz LVPECL clock output
Additive output jitter 225 fs rms
800 MHz/250 MHz LVDS/CMOS clock output
Additive output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
FUNCTIONAL BLOCK DIAGRAM
VREF
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1
S0
SETUP LOGIC
OUT0
CLK
CLKB
SYNCB
RSET VS GND
OUT0B
OUT1
OUT1B
AD9515
/1. . . /32
/1. . . /32
∆
t
LVPECL
LVDS/CMOS
05597-001
Figure 1.
GENERAL DESCRIPTION
The AD9515 features a two-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit
from this part.
There are two independent clock outputs. One output is
LVPECL, while the other output can be set to either LVDS or
CMOS levels. The LVPECL output operates to 1.6 GHz. The
other output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to the other clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9515 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ V
S
. The VREF pin provides a level of
⅔ V
S
. V
S
(3.3 V) and GND (0 V) provide the other two logic levels.
The AD9515 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9515 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to +85°C.
AD9515* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
EVALUATION KITS
• AD9515 Evaluation Board
DOCUMENTATION
Application Notes
• AN-0974: Multicarrier TD-SCMA Feasibility
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-769: Generating Multiple Clock Outputs from the
AD9540
• AN-823: Direct Digital Synthesizers in Clocking
Applications Time
• AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
• AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
• AN-927: Determining if a Spur is Related to the DDS/DAC
or to Some Other Source (For Example, Switching
Supplies)
• AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
Data Sheet
• AD9515: 1.6 GHz Clock Distribution IC, Dividers, Delay
Adjust, Two Outputs Data Sheet
TOOLS AND SIMULATIONS
• ADIsimCLK Design and Evaluation Software
• AD9515 IBIS Models
REFERENCE DESIGNS
• CN0109
REFERENCE MATERIALS
Press
• Analog Devices’ Dual 14-bit A/D Converter Reduces
Power and Size in Communications, Instrumentation, Test
and Measurement Applications
Product Selection Guide
• RF Source Booklet
Technical Articles
• ADI Buys Korean Mobile TV Chip Maker
• Design A Clock-Distribution Strategy With Confidence
• Improved DDS Devices Enable Advanced Comm Systems
• Low-power direct digital synthesizer cores enable high
level of integration
• Speedy A/Ds Demand Stable Clocks
• Understand the Effects of Clock Jitter and Phase Noise on
Sampled Systems
DESIGN RESOURCES
• AD9515 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONS
View all AD9515 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD9515 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Clock Input .................................................................................... 3
Clock Outputs ............................................................................... 3
Timing Characteristics ................................................................ 4
Clock Output Phase Noise .......................................................... 5
Clock Output Additive Time Jitter ............................................. 8
SYNCB, VREF, and Setup Pins ................................................... 9
Power ............................................................................................ 10
Timing Diagrams ............................................................................ 11
Absolute Maximum Ratings .......................................................... 12
Thermal Characteristics ............................................................ 12
ESD Caution ................................................................................ 12
Pin Configuration and Function Descriptions ........................... 13
Terminology .................................................................................... 14
Typical Performance Characteristics ........................................... 15
Functional Description .................................................................. 18
Overall .......................................................................................... 18
CLK, CLKB—Differential Clock Input ................................... 18
Synchronizat ion .......................................................................... 18
R
SET
Resistor ................................................................................ 19
VREF ............................................................................................ 19
Setup Configuration................................................................... 19
Programming .................................................................................. 20
Divider Phase Offset .................................................................. 22
Delay Block ................................................................................. 22
Outputs ........................................................................................ 23
Power Supply ............................................................................... 23
Power Management ................................................................... 24
Applications ..................................................................................... 25
Using the AD9515 Outputs for ADC Clock Applications .... 25
LVPECL Clock Distribution ..................................................... 25
LVDS Clock Distribution .......................................................... 26
CMOS Clock Distribution ........................................................ 26
Setup Pins (S0 to S10) ................................................................ 26
Power and Grounding Considerations and Power Supply
Rejection ...................................................................................... 26
Phase Noise and Jitter Measurement Setups ........................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
4/12—Rev. 0 to Rev. A
Changes to Table 9 .......................................................................... 13
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
7/05—Revision 0: Initial Version
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

AD9515BCPZ

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Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution 1.6GHz Dividers Delay Adj 2 Outputs
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