AD9515 Data Sheet
Rev. A | Page 12 of 28
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter or Pin
With
Respect
to Min Max Unit
VS GND −0.3 +3.6 V
RSET GND −0.3 V
S
+ 0.3 V
CLK, CLKB GND −0.3 V
S
+ 0.3 V
CLK CLKB −1.2 +1.2 V
OUT0, OUT0B, OUT1, OUT1B GND −0.3 V
S
+ 0.3 V
Junction Temperature
1
150 °C
Storage Temperature −65 +150 °C
Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
2
Thermal Resistance
32-Lead LFCSP
3
θ
JA
= 36.6°C/W
1
See Thermal Characteristics for θ
JA
.
2
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-7.
3
The external pad of this package must be soldered to adequate copper land
on board.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the
human body and test equipment and can discharge without detection. Although this product features
proprietary E
SD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Data Sheet AD9515
Rev. A | Page 13 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1VS
2CLK
3CLKB
4VS
5SYNCB
6VREF
7S10
8S9
18 OUT1B
19 OUT1
20 VS
21 VS
22 OUT0B
23 OUT0
24 VS
17 VS
9S8
10S7
11S6
13S4
15S2
14S3
16S1
12S5
26
VS
27
DNC
28
DNC
29
VS
30
VS
25
S0
TOP VIEW
(Not to Scale)
AD9515
31
GND
32
RSET
05597-005
Figure 6. 32-Lead LFCSP Pin Configuration
05597-006
1
32
8
9
25
24
16
17
THE EXPOSED PADDLE
IS AN ELECTRICAL AND
THERMAL CONNECTION
EXPOSED PAD
(BOTTOM VIEW)
GND
Figure 7. Exposed Paddle
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1, 4, 17, 20, 21, 24, 26, 29, 30 VS Power Supply (3.3 V).
2 CLK Clock Input.
3 CLKB Complementary Clock Input. Used in conjunction with CLK.
5 SYNCB Used to Synchronize the Outputs; Active Low Signal.
6
VREF
Provides 2/3 V
S
Reference Voltage for Use with Programming Pins S0 to S10.
25, 16, 15, 14, 13, 12, 11, 10, 9,
8, 7
S0 to S10 Programming Pins. These pins determine the operation of the AD9515; 4-state logic.
18 OUT1B Complementary LVDS/Inverted CMOS Output. Includes a delay block.
19 OUT1 LVDS/CMOS Output. Includes a delay block.
22 OUT0B Complementary LVPECL Output.
23 OUT0 LVPECL Output.
27, 28 DNC Do Not Connect.
31, Exposed Paddle GND Ground. The exposed paddle on the back of the chip is also GND.
32 RSET Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.
AD9515 Data Sheet
Rev. A | Page 14 of 28
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 to 360 degrees
for each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although there are many
causes that can contribute to phase jitter, one major component
is due to random noise that is characterized statistically as being
Gaussian (normal) in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is also meaningful to integrate the total power contained
within some interval of offset frequencies (for example, 10 kHz
to 10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency
interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. For a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Since these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the SNR and dynamic range of the converter. A
sampling clock with the lowest possible jitter provides the
highest performance from a given converter.
Additive Phase Noise
It is the amount of phase noise that is attributable to the device
or subsystem being measured. The phase noise of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device affects the
total system phase noise when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own phase noise to the total. In many cases, the phase
noise of one element dominates the system phase noise.
Additive Time Jitter
It is the amount of time jitter that is attributable to the device or
subsystem being measured. The time jitter of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device will affect the
total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.

AD9515BCPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution 1.6GHz Dividers Delay Adj 2 Outputs
Lifecycle:
New from this manufacturer.
Delivery:
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